The transversal and longitudinal resistance in the quantum Hall effect regime was measured in a Si MOSFET sample in which a slot-gate allows one to vary the electron density and filling factor in different parts of the sample. In case of unequal gate voltages, the longitudinal resistances on the opposite sides of the sample differ from each other because the originated Hall voltage difference is added to the longitudinal voltage only on one side depending on the gradient of the gate voltages and the direction of the external magnetic field. After subtracting the Hall voltage difference, the increase in longitudinal resistance is observed when electrons on the opposite sides of the slot occupy Landau levels with different spin orientations.
We report measurements on a Si-MOSFET sample with a slot in the upper gate, allowing for different electron densities n_{1,2} across the slot. The dynamic longitudinal resistance was measured by the standard lock-in technique, while maintaining a large DC current through the source-drain channel. We find that the conductance of the sample in a strong parallel magnetic field is asymmetric with respect to the DC current direction. This asymmetry increases with magnetic field. The results are interpreted in terms of electron spin accumulation or depletion near the slot.
The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a high mobility In0.53Ga0.47As channel and atomic-layer-deposited (ALD) Al2O3/WN gate stacks by a top-down approach. A well-controlled InGaAs nanowire release process and a novel ALD high-k/metal gate process has been developed to enable the fabrication of III-V GAA MOSFETs. Well-behaved on-state and off-state performance has been achieved with channel length (Lch) down to 50nm. A detailed scaling metrics study (S.S., DIBL, VT) with Lch of 50nm - 110nm and fin width (WFin) of 30nm - 50nm are carri…
A widely used technique to mitigate the gate leakage in the ultra-scaled metal oxide semiconductor field effect transistors (MOSFETs) is the use of high-k dielectrics, which provide the same equivalent oxide thickness (EOT) as $\rm SiO_2$, but thicker physical layers. However, using a thicker physical dielectric for the same EOT has a negative effect on the device performance due to the degradation of 2D electrostatics. In this letter, the effects of high-k oxides on double-gate (DG) MOSFET with the gate length under 20 nm are studied. We find that there is an optimum physical oxide thickness …
In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, Dual Material Double Gate (DMDG) SOI MOSFET, exhibits significantly reduced short channel effects when compared with the DG SOI MOSFET. Short channel effects in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, e…
A compact model for the effect of parasitic internal fringe capacitance on threshold voltage in high-K gate dielectric SOI MOSFETs is developed. Our model includes the effects of the gate dielectric permittivity, spacer oxide permittivity, spacer width, gate length and width of MOS structure. A simple expression for parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. We demonstrate an increase in surface potential along the channel due to these charges result…
Ambipolar black phosphorus MOSFETs with record n-channel extrinsic transconductance are reported. The devices consist of multi-layer black phosphorus aligned to a local back-gate electrode with 10-nm-thick HfO2 gate dielectric. Before passivation, devices with 0.3-um gate length behaved as p-MOSFETs with peak extrinsic transconductance, gm, of 282 uS/um at VDS = -2 V. After passivation, the same devices displayed ambipolar behavior, and when tested as n-MOSFETs, had peak gm = 66 uS/um at VDS = +2 V, and similar devices on the same wafer had gm as high as 80 uS/um. These results are an importan…
The trench gate MOSFET has established itself as the most suitable power device for low to medium power applications by offering the lowest possible ON resistance among all MOS devices. The evolution of the trench gate power MOSFET has been discussed in this chapter, starting right from its beginnings to the recent trends. The innovations in the structural improvements to meet the requirements for an efficient operation, the progress in the fabrication technology, the characterization methods and various reliability issues have been emphasized.
The tremendous progress in Metal Oxide Semiconductor (MOS) technology has been a direct consequence of device scaling for past several decades. But as we have entered the nanometer era many problems related to leakage currents and other issues related to variability impacting the yield are of concern. Herein we have investigated how the change in the Fin Architecture and Gate Length of the MOS device impacts the Threshold Voltage.
InGaAs gate-all-around nanowire MOSFETs with channel length down to 50nm have been experimentally demonstrated by top-down approach. The nanowire size-dependent transport properties have been systematically investigated. It is found that reducing nanowire dimension leads to higher on-current, transconductance and effective mobility due to stronger quantum confinement and the volume inversion effect. TCAD quantum mechanical simulation has been carried out to study the inversion charge distribution inside the nanowires. Volume inversion effect appears at a larger dimension for InGaAs nanowire MO…
We report the fabrication and study of Hall bar MOSFET devices in which an overlapping-gate architecture allows four-terminal measurements of low-density 2D electron systems, while maintaining a high density at the ohmic contacts. Comparison with devices made using a standard single gate show that measurements can be performed at much lower densities and higher channel resistances, despite a reduced peak mobility. We also observe a voltage threshold shift which we attribute to negative oxide charge, injected during electron-beam lithography processing.
Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI MOSFET will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50 nm. We conclude that if the side gate length equals the main gate length, the hot electron effect diminishes optimally.
We report record performance for black phosphorus p-MOSFETs. The devices have locally patterned back gates and 20-nm-thick HfO2 gate dielectrics. Devices with effective gate length, Leff = 1.0 um display extrinsic transconductance, gm, of 101 uS/um at a drain-to-source bias voltage, Vds = -3 V. Temperature-dependent analysis also shows that the subthreshold slope, SS, is nearly ideal, with a minimum value of SS = 66 mV/decade at room temperature and Vds = -0.1 V. Furthermore, devices with 7-nm HfO2 dielectrics and Leff = 0.3 um displayed gm as high as 204 uS/um at Vds = -1.5 V.
In this paper, we have experimentally demonstrated, for the first time, III-V 4D transistors with vertically stacked InGaAs nanowire (NW) channels and gate-all-around (GAA) architecture. Novel process technology enabling the transition from 3D to 4D structure has been developed and summarized. The successful fabrication of InGaAs lateral and vertical NW arrays has led to 4x increase in MOSFET drive current. The top-down technology developed in this paper has opened a viable pathway towards future low-power logic and RF transistors with high-density III-V NWs.
We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily-doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4,000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate ox…
This paper depicts the actual variation of gate induced drain leakage current with impurity doping concentration by complete qualitative and quantitative approach. De Casteljaus algorithm is applied to describe the band to band tunneling in a thin gate oxide nMOSFET and the results are remarkably matched. Moreover for the very first time, the dependency of the leakage current over impurity density in the MOSFET drain region is explained in the context of pure geometrical approach. Surprisingly one of the proportionality constant exactly behaves like impurity gradient which results same charact…
In this paper, 20nm - 80nm channel length (Lch) InGaAs gate- all-around (GAA) nanowire MOSFETs with record high on- state and off-state performance have been demonstrated by equivalent oxide thickness (EOT) and nanowire width (WNW) scaling down to 1.2nm and 20nm, respectively. SS and DIBL as low as 63mV/dec and 7mV/V have been demonstrated, indicating excellent interface quality and scalability. Highest ION = 0.63mA/μm and gm = 1.74mS/μm have also been achieved at VDD=0.5V, showing great promise of InGaAs GAA technology for 10nm and beyond high-speed low- power logic applications.
We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range 7-17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300 K and at 1.6 K between the top and back interfaces of the Si well, which is interpreted to arise fro…
Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS FPGA for 22nm, 32nm and 45nm technologies including 20% transistor size variation. We show that area is reduced and speed is increased in spin FPGA owing to the nonvolatile memory function of spin MOSFET.
A common issue in low temperature measurements of enhancement-mode metal-oxide-semiconductor (MOS) field-effect transistors (FETs) in the low electron density regime is the high contact resistance dominating the device impedance. In that case a voltage bias applied across the source and drain contact of a Hall bar MOSFET will mostly fall across the contacts (and not across the channel) and therefore magneto-transport measurements become challenging. However, from a physical point of view, the study of MOSFET nanostructures in the low electron density regime is very interesting (impurity limite…
High performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (Lch) down to 20nm have been fabricated by integrating a higher-k LaAlO3-based gate stack with an equivalent oxide thickness of 1.2nm. It is found that inserting an ultrathin (0.5nm) Al2O3 interfacial layer between higher-k and InGaAs can significantly improve the interface quality and reduce device variation. As a result, a record low subthreshold swing of 63mV/dec has been demonstrated at sub-80nm Lch for the first time, making InGaAs GAA nanowire devices a strong candidate for future low-power transistors.
A gate voltage application in a Si-based spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) modulates spin accumulation voltages, where both electrical conductivity and drift velocity are modified while keeping constant electric current. An unprecedented reduction in the spin accumulation voltages in a Si spin MOSFET under negative gate voltage applications is observed in a high electric bias current regime. To support our claim, the electric bias current dependence of the spin accumulation voltage under the gate voltage applications is investigated in detail and compared to …
The scattering effects are studied in nanometer-scaled double-gate MOSFET, using Monte Carlo simulation. The non-equilibrium transport in the channel is analyzed with the help of the spectroscopy of the number of scatterings experienced by electrons. We show that the number of ballistic electrons at the drain end, even in terms of flux, is not the only relevant characteristic of ballistic transport. Then the drive current in the 15 nm-long channel transistor generations should be very close to the value obtained in the ballistic limit even if all electrons are not ballistic. Additionally, most…
In this paper, a two-dimensional analytical model of a laterally graded-channel triple-metal double-gate Junctionless Field Effect Transistor with hetero dielectric gate oxide stack consisting of SiO$_2$ and HfO$_2$ is derived. The model illustrates higher drive current and better performance against hazardous SCEs and HCEs in below 30 nm regime. Parabolic approximation method is used here to construct channel potentials and electric fields by solving 2-D Poisson's equation with applicable boundary conditions. The basic central and surface potentials as well as central and surface electric fie…
For the first time, thousands of RF MOSFETs were batch-fabricated on liquid-exfoliated MoS2 below 300 °C with nearly 100% yield. The large-scale fabrication with high yield allowed the average performance instead of the best performance to be reported. The DC performance of these devices were typical, but the RF performance, enabled by buried gates and on the order of 100 MHz, was reported for the first time for liquid-exfoliated MoS2. To resolve the dilemma of thin vs. thick films, gate recess was used on 20-nm thick films to improve the gate control while keeping the contact resistance lower…
We study the transport properties of monolayer MX2 (M = Mo, W; X = S, Se, Te) n- and p- channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic non-equilibrium Green's function simulations with an atomistic tight-binding Hamiltonian with hopping potentials obtained from density functional theory. We discuss the subthreshold slope, drain-induced barrier lowering (DIBL), as well as gate-induced drain leakage (GIDL) for different monolayer MX2 MOSFETs. We also report the possibility of negative differential resistance behavior in the output characteristics o…
In the race towards high-performance ultra-scaled devices, two-dimensional materials offer an alternative paradigm thanks to their atomic thickness suppressing short-channel effects. It is thus urgent to study the most promising candidates in realistic configurations, and here we present detailed multiscale simulations of field-effect transistors based on arsenene and antimonene monolayers as channels. The accuracy of first-principles approaches in describing electronic properties is combined with the efficiency of tight-binding Hamiltonians based on maximally-localised Wannier functions to co…
Spin transport in non-degenerate semiconductors is expected to pave a way to the creation of spin transistors, spin logic devices and reconfigurable logic circuits, because room temperature (RT) spin transport in Si has already been achieved. However, RT spin transport has been limited to degenerate Si, which makes it difficult to produce spin-based signals because a gate electric field cannot be used to manipulate such signals. Here, we report the experimental demonstration of spin transport in non-degenerate Si with a spin metal-oxide-semiconductor field-effect transistor (MOSFET) structure.…
In this letter we not only show improvement in the performance but also in the reliability of 30nm thick biaxially strained SiGe (20%Ge) channel on Si p-MOSFETs. Compared to Si channel, strained SiGe channel allows larger hole mobility (μh) in the transport direction and alleviates charge flow towards the gate oxide. μh enhancement by 40% in SiGe and 100% in Si-cap SiGe is observed compared to the Si hole universal mobility. A ~40% reduction in NBTI degradation, gate leakage and flicker noise (1/f) is observed which is attributed to a 4% increase in the hole-oxide barrier height (ϕ) in SiGe. S…
In this work we propose a fully experimental method to extract the barrier lowering in short-channel saturated MOSFETs using the Lundstrom backscattering transport model in a one sub-band approximation and carrier degeneracy. The knowledge of the barrier lowering at the operative bias point in the inversion regime is of fundamental importance in device scaling. At the same time we obtain also an estimate of the backscattering ratio and of the saturation inversion charge. Respect to previously reported works on extraction of transport parameters based on the Lundstrom model, our extraction meth…
We investigate the role of electron-phonon scattering and gate bias in degrading the drive current of nanotube MOSFETs. Our central results are: (i) Optical phonon scattering significantly decreases the drive current only when gate voltage is higher than a well-defined threshold. It means that elastic scattering mechanisms are most detrimental to nanotube MOSFETs. (ii) For comparable mean free paths, a lower phonon energy leads to a larger degradation of drive current. Thus for semiconducting nanowire FETs, the drive current will be more sensitive than carbon nanotube FETs because of the small…
In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) = \ln10~k_BT/e$. However, recent low-temperature studies of different advanced CMOS technologies have reported $SS$(4K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of $SS(T)$ in 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxi…
We incorporate an Al-AlO_x-Al single-electron transistor as the gate of a narrow (~100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET). Near the MOSFET channel conductance threshold, we observe oscillations in the conductance associated with Coulomb blockade in the channel, revealing the formation of a Si single-electron transistor. Abrupt steps present in sweeps of the Al transistor conductance versus gate voltage are correlated with single-electron charging events in the Si transistor, and vice versa. Analysis of these correlations using a simple electrostatic model demonstrat…
Few-layer phosphorene MOSFETs with 0.3-um-long gate and 15-nm-thick Al2O3 gate insulator was found to exhibit a forward-current cutoff frequency of 2 GHz and a maximum oscillation frequency of 8 GHz after de-embedding for the parasitic capacitance associated mainly with the relatively large probe pads. The gate lag and drain lag of the transistor was found to be on the order of 1 us or less, which is consistent with the lack of hysteresis, carrier freeze-out or persistent photoconductivity in DC characteristics. These results confirm that the phosphorene MOSFET can be a viable microwave transi…
We investigate coherent transport in Si:MOSFETs with nominal gate lengths 50 to 100nm and various widths at very low temperature. Independent of the geometry, localized states appear when G=e^{2}/h and transport is dominated by resonant tunnelling through a single quantum dot formed by an impurity potential. We find that the typical size of the relevant impurity quantum dot is comparable to the channel length and that the periodicity of the observed Coulomb blockade oscillations is roughly inversely proportional to the channel length. The spectrum of resonances and the nonlinear I-V curves all…
This paper addresses the question of whether a ``rigid molecule'' (one which does not deform in an external field) used as the conducting channel in a standard three-terminal MOSFET configuration can offer any performance advantage relative to a standard silicon MOSFET. A self-consistent solution of coupled quantum transport and Poisson's equations shows that even for extremely small channel lengths (about 1 nm), a ``well-tempered'' molecular FET demands much the same electrostatic considerations as a ``well-tempered'' conventional MOSFET. In other words, we show that just as in a conventional…
We review a series of works describing thermoelectric effects in gated disordered nanowires (field effect transistor device configuration). After considering the elastic coherent regime characterizing sub-Kelvin temperatures, we study the inelastic activated regime occurring at higher temperatures, where electronic transport is dominated by phonon-assisted hops between localised states (Mott variable range hopping). The thermoelectric effects are studied as a function of the location of the Fermi level inside the nanowire conduction band, notably around its edges where they become very large. …
Spin-based metal-oxide-semiconductor field-effect transistors (MOSFET) with a high-mobility III-V channel are studied using self-consistent quantum corrected ensemble Monte Carlo device simulations of charge and spin transport. The simulations including spin-orbit coupling mechanisms (Dresselhaus and Rashba coupling) examine the electron spin transport in the 25 nm gate length In$_{0.7}$Ga$_{0.3}$As MOSFET. The transistor lateral dimensions (the gate length, the source-to-gate, and the gate-to-drain spacers) are increased to investigate the spin-dependent drain current modulation induced by th…
This paper discusses the influence of the channel impurity distribution on the transport and the drive current in short-gate MOSFET. In this purpose, a careful description of electron-ion interaction suitable for the case of discrete impurities has been implemented in a 3D particle Monte Carlo simulator. This transport model is applied to the investigation of 50 nm MOSFET operation. The results show that a small change in the number of doping impurities or in the position of a single discrete impurity in the inversion layer may significantly influence the drain current. This effect is not only…
We analyze the distributions of electric potential and field, polarization and charge, and the differential capacitance of a silicon metal-oxide-ferroelectric field effect transistor (MOSFET), in which a gate insulator consists of thin layers of dielectric SiO2 and weak ferroelectric HfO2. It appeared possible to achieve a quasi-steady-state negative capacitance of the HfO2 layer, C_(HfO_2 )<0, if the layer thickness is close to the critical thickness of the size-induced ferroelectric-paraelectric phase transition. The quasi-steady-state negative capacitance, being a very slow-varying transien…
A model is developed for a detailed investigation of the current flowing through a cylindrical nanosize MOSFET with a close gate electrode. The quantum mechanical features of the lateral charge transport are described by Wigner distribution function which is explicitly dealing with electron scattering due to acoustic phonons and acceptor impurities. A numerical simulation is carried out to obtain a set of I-V characteristics for various channel lengths. It is demonstrated that inclusion of the collision term in the numerical simulation is important for low values of the source-drain voltage. T…
Spin-transport characteristics in a Si-based spin metal-oxide-semiconductor field-effect transistor (spin MOSFET): Bias dependence of the spin polarization in Si and magnetoresistance in spin-valve signals
Doping is a common route to reducing nanowire transistor on-resistance but has limits. High doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even when the Be doping in our GaAs nanowires is so high that traditional metal-oxide gates fail. In this regime we obtain a combination of sub-threshold swing and contact resistance that surpasses the best existing p-type nanowire MOSFETs. Our sub-threshold swing of 75 mV/dec is within 25% of the room-temperature thermal limit and comparable with n-InP and n-Ga…
We have performed conductivity measurements on a Si-MOSFET sample with a slot in the upper gate, allowing for different electron densities n_1 and n_2 across the slot. Dynamic longitudinal resistance was measured by a standard lock-in technique, while maintaining a large DC current through the source-drain channel. We find that in a parallel magnetic field, the resistance of the sample, R(I_DC), is asymmetric with respect to the direction of the DC current. The asymmetry becomes stronger with an increase of either the magnetic field or the difference between n_1 and n_2. These observations are…
We study the transport properties of deeply scaled monolayer MoS2 n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic quantum transport simulations with an atomistic tight-binding Hamiltonian obtained from density functional theory. Our simulations suggest that monolayer MoS2 MOSFETs can provide near-ideal subthreshold slope, and suppression of drain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL). However, these full-band simulations also exhibit limited transconductance. These ballistic simulations also exhibit negative diffe…
Metal-oxide-semiconductor field-effect transistors (MOSFET's) using atomic-layer-deposited (ALD) Al$_2$O$_3$ as the gate dielectric are fabricated on the Si/Si$_{1-x}$Ge$_x$ heterostructures. The low-temperature carrier density of a two-dimensional electron system (2DES) in the strained Si quantum well can be controllably tuned from 2.5$\times10^{11}$cm$^{-2}$ to 4.5$\times10^{11}$cm$^{-2}$, virtually without any gate leakage current. Magnetotransport data show the homogeneous depletion of 2DES under gate biases. The characteristic of vertical modulation using ALD dielectric is shown to be bet…
In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-\k{appa} gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating voltage of 0.5 V. Using calibrated two-dimensional simulations it is shown that even for such a low operating voltage, the gate leakage substantially degrades several subthreshold parameters of the TFET such as the off-state current, minimum subthreshold swing and average subthreshold swing. While the drain-offset as well as the short-gate are effective methods…
The operation of an integrated two-dimensional complementary metal-oxide-semiconductor inverter with well-matched input/output voltages is reported. The circuit combines a few-layer MoS2 n-MOSFET and a black phosphorus (BP) p-MOSFET fabricated using a common local backgate electrode with thin (20 nm) HfO2 gate dielectric. The constituent devices have linear threshold voltages of -0.8 V and +0.8 V and produce peak transconductances of 16 uS/um and 41 uS/um for the MoS2 n-MOSFET and BP p-MOSFET, respectively. The inverter shows a voltage gain of 3.5 at a supply voltage, VDD = 2.5 V, and has peak…
We wish to report in this paper a study of the effective mass (m^*) in thin-oxide Si-metal-oxide-semiconductor field-effect-transistors, using the temperature dependence of the Shubnikov-de Haas (SdH) effect and following the methodology developed by J.L. Smith and P.J. Stiles, Phys. Rev. Lett. {\bf 29}, 102 (1972). We find that in the thin oxide limit, when the oxide thickness $d_{ox}$ is smaller than the average two-dimensional electron-electron separation r, m^* is still enhanced and the enhancement can be described by $m^*/m_B = 0.815 + 0.23(r/d_{ox})$, where $m_B = 0.195 m_e$ is the bulk …
Thermally activated sub-threshold transport has been investigated in undoped triple gate MOSFETs. The evolution of the barrier height and of the active cross-section area of the channel as a function of gate voltage has been determined. The results of our experiments and of the Tight Binding simulations we have developed are both in good agreement with previous analytical calculations, confirming the validity of thermionic approach to investigate transport in FETs. This method provides an important tool for the improvement of devices characteristics.
An Al-AlO_x-Al single-electron transistor (SET) acting as the gate of a narrow (~ 100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET) can induce a vertically aligned Si SET at the Si/SiO_2 interface near the MOSFET channel conductance threshold. By using such a vertically coupled Al and Si SET system, we have detected a single-charge defect which is tunnel-coupled to the Si SET. By solving a simple electrostatic model, the fractions of each coupling capacitance associated with the defect are extracted. The results reveal that the defect is not a large puddle or metal island, but…
