An Al-AlO_x-Al single-electron transistor (SET) acting as the gate of a narrow (~ 100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET) can induce a vertically aligned Si SET at the Si/SiO_2 interface near the MOSFET channel conductance threshold. By using such a vertically coupled Al and Si SET system, we have detected a single-charge defect which is tunnel-coupled to the Si SET. By solving a simple electrostatic model, the fractions of each coupling capacitance associated with the defect are extracted. The results reveal that the defect is not a large puddle or metal island, but its size is rather small, corresponding to a sphere with a radius less than 1 nm. The small size of the defect suggests it is most likely a single-charge trap at the Si/SiO_2 interface. Based on the ratios of the coupling capacitances, the interface trap is estimated to be about 20 nm away from the Si SET.
We have investigated the gate-voltage dependence and the temperature dependence of the magnetoconductivity of amorphous indium-gallium-zinc-oxide thin-film transistors. A weak-localization feature is observed at small magnetic fields on top of an overall negative magnetoconductivity at higher fields. An intriguing controllable competition between weak localization and weak antilocalization is observed by tuning the gate voltage or varying the temperature. Our findings reflect controllable quantum interference competition in the electron systems in amorphous indium-gallium-zinc-oxide thin-film …
In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect- Transistor (MOSFET) in which the front gate consists of two materials with different work functions.
We demonstrate high yield fabrication of field effect transistors (FET) using chemically reduced graphene oxide (RGO) sheets suspended in water assembled via dielectrophoresis. The two terminal resistances of the devices were improved by an order of magnitude upon mild annealing at 200 0C in Ar/H2 environment for 1 hour. With the application of a backgate voltage, all of the devices showed FET behavior with maximum hole and electron mobilities of 4.0 and 1.5 cm2/Vs respectively. This study shows promise for scaled up fabrication of graphene based nanoelectronic devices.
Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the non-equilibrium Green's functions formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (Y. Lu et al, J. Am. Chem. Soc., v. 128, p. 3518-3519, 2006), we have obtained strong evidence that BTBT in CNT-MOSFETs is dominated by…
We study hole spin resonance in a p-channel silicon metal-oxide-semiconductor field-effect transistor. In the sub-threshold region, the measured source-drain current reveals a double dot in the channel. The observed spin resonance spectra agree with a model of strongly coupled two-spin states in the presence of a spin-orbit-induced anti-crossing. Detailed spectroscopy at the anti-crossing shows a suppressed spin resonance signal due to spin-orbit-induced quantum state mixing. This suppression is also observed for multi-photon spin resonances. Our experimental observations agree with theoretica…
We describe a measurement method that enables the correct estimation of the charging energy of an unintentional quantum dot (QD) in the channel of a metal-oxide-semiconductor field-effect transistor (MOSFET). If the channel has a dominant QD with a large charging energy and an array of stray QDs with much weaker charging, this method eliminates the additional voltage drops due to stray QDs by regarding the stray QDs as series resistors. We apply this method to a short-channel MOSFET and find that the charging energy of the dominant QD can indeed be smaller than the size of the Coulomb diamond.
The carrier mobility μof few-layer graphene (FLG) field-effect transistors increases ten-fold when the SiO_2 substrate is replaced by single-crystal epitaxial Pb(Zr_0.2Ti_0.8)O_3 (PZT). In the electron-only regime of the FLG, μreaches 7x10^4 cm^2/Vs at 300K for n = 2.4x10^12/cm^2, 70% of the intrinsic limit set by longitudinal acoustic (LA) phonons; it increases to 1.4x10^5 cm^2/Vs at low temperature. The temperature-dependent resistivity ρ(T) reveals a clear signature of LA phonon scattering, yielding a deformation potential D = 7.8+/-0.5 eV.
Supplementary Information to arXiv:0810.4466: 1. Characterizations of Pb(Zr_0.2Ti_0.8)O_3 (PZT) films. 2. Substrate preparation before the exfoliation of graphene. 3. The band structure of FLG. 4. Dielectric constant measurements of PZT. 5. rho(V_g) and R_H(V_g) fitting inside the band overlap regime. 6. The deformation potential of longitudinal acoustic (LA) phonons in graphene. 7. Resistivity and Hall measurements of a SiO_2-gated FLG.
We demonstrate a tunnel field effect transistor based on a lateral heterostructure patterned from an $\mathrm{LaAlO_3/SrTiO_3}$ electron gas. Charge is injected by tunneling from the $\mathrm{LaAlO_3}$/$\mathrm{SrTiO_3}$ contacts and the current through a narrow channel of insulating $\mathrm{SrTiO_3}$ is controlled via an electrostatic side gate. Drain-source I/V-curves have been measured at low and elevated temperatures. The transistor shows strong electric-field and temperature-dependent behaviour with a steep sub-threshold slope %of up to as small as $10\:\mathrm{mV/decade}$ and a transcon…
In this letter, it is shown that the existing scaling theories for chemically doped transistors cannot be applied to the novel class of electrically doped 2D transistors and the concept of equivalent oxide thickness (EOT) is not applicable anymore. Hence, a novel scaling theory is developed based on analytic solutions of the 2D Poisson equation. Full band atomistic quantum transport simulations verify the theory and show that the critical design parameters are the physical oxide thickness and distance between the gates. Accordingly, the most optimized electrically doped devices are those with …
We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 $\times$ 20 nm$^{2}$ is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement…
We demonstrate top-gated field effect transistor made of reduced graphene oxide (RGO) monolayer (graphene) by dielectrophoresis. Raman spectrum of RGO flakes of typical size of 5μm x 5μm show a single 2D band at 2687 cm-1, characteristic of a single layer graphene. The two probe current - voltage measurements of RGO flakes, deposited in between the patterned electrodes with a gap of 2.5 μm using a.c. dielectrophoresis show ohmic behavior with a resistance of ~ 37kΩ. The temperature dependence of the resistance (R) of RGO measured between temperatures 305 K to 393 K yields temperature coefficie…
A large variability of carrier mobility of graphene-based field effect transistors hampers graphene science and technology. We determine the scattering strength of the dominant scatterer responsible for the variability of graphene-based transistors on silicon oxide. The strength of the scatterer is found to be more consistent with charged impurities than with resonant impurities.
We report the field emission (FE) properties of Cu coated vertically aligned carbon nanotubes (VACNTs) before and after oxidation. The current density was found to be the maximum (20 mA/cm$^2$) for 3 nm thick Cu coated VACNTs after oxidation. The variation in conventionally monitored parameters like work function and field enhancement factor does not explain the experimentally determined FE current density. A critical analysis of the electronic structure reveals the importance of presence of Cu$_2$O at the interface of CuO and VACNTs, which in turn controls the current density of these films. …
We propose a modified spin-field-effect transistor fabricated in a two dimensional electron gas (2DEG) formed at the surface of multiferroic oxides with a transverse helical magnetic order. The topology of the oxide local magnetic moments induces a resonant momentum-dependent effective spin-orbit interaction acting on 2DEG. We show that spin polarization dephasing is strongly suppressed which is crucial for functionality. The carrier spin precession phase depend linearly on the magnetic spiral helicity. The latter is electrically controllable by virtue of the magento-electric effect. We also s…
Using 2-D self-consistent ballistic quantum transport simulations, we investigate the short-channel behavior of graphene field-effect transistors and its impact on the device transconductance and subsequently the intrinsic cut-off frequency (fT). Although with thin oxides, fT expectedly scales inversely with the gate length, significant band-to-band tunneling at OFF state leads to a departure from this trend in case of thick oxides. We also examine the effect of achieving better electrostatics at the cost of increased gate capacitance and illustrate that this can indeed degrade the fT. These c…
A spin metal-oxide-semiconductor field-effect-transistor (spin MOSFET), which combines a Schottky-barrier MOSFET with ferromagnetic source and drain contacts, is a promising device for spintronic logic. Previous simulation studies predict that this device should display a very high magnetoresistance (MR) ratio (between the cases of parallel and anti-parallel magnetizations) for the case of half-metal ferromagnets (HMF). We use the non-equilibrium Green's function (NEGF) formalism to describe tunneling and carrier transport in this device and to incorporate spin relaxation at the HMF-semiconduc…
The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2/Vs in ambient conditions, which we attribute to the …
Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuron transistors gated by solid-state electrolyte films are fabricated on flexible plastic substrates for biochemical sensing applications. When a quasi-static dual-gate laterally synergic sensing mode is adopted, the neuron transistor sensor shows a high pH sensitivity of ~105 mV/pH, which is higher than the Nernst limit. Our results demonstrate that single-spike dynamic mode can remarkably improve the pH sensitivity, reduce response/recover time and power consumption. We also find that …
We report silicon delta doping in Gallium Oxide (\b{eta}-Ga2O3) grown by plasma assisted molecular beam epitaxy using a shutter pulsing technique. We describe growth procedures that can be used to realize high Si incorporation in an oxidizing oxygen plasma environment. Delta doping was used to realize thin (12 nm) low-resistance layers with sheet resistance of 320 Ohm/square (mobility of 83 cm^2/Vs, integrated sheet charge of 2.4x10^14 cm^-2). A single delta-doped sheet of carriers was employed as a channel to realize a field effect transistor with current ID,MAX =292 mA/mm and transconductanc…
In this work, we demonstrate scaled back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by atomic layer deposition (ALD) with channel thickness (Tch) of 1.0-1.5 nm, channel length (Lch) down to 40 nm, and equivalent oxide thickness (EOT) of 2.1 nm, with record high drain current of 2.0 A/mm at VDS of 0.7 V among all oxide semiconductors. Enhancement-mode In2O3 transistors with ID over 1.0 A/mm at VDS of 1 V are also achieved by controlling the channel thickness down to 1.0 nm at atomic layer scale. Such high current density in a relatively low mobility amorphous oxide semicondu…
Band structure of InSb thin films with $<100>$ surface orientation is calculated using empirical pseudopotential method (EPM) to evaluate the performance of nanoscale devices using InSb substrate. Contrary to the predictions by simple effective mass approximation methods (EMA), our calculation reveals that $Γ$ valley is still the lowest lying conduction valley. Based on EPM calculations, we obtained the important electronic structure and transport parameters, such as effective mass and valley energy minimum, of InSb thin film as a function of film thickness. Our calculations reveal that the 'e…
Results of quantum mechanical simulations of the influence of edge disorder on transport in graphene nanoribbon metal oxide semiconductor field-effect transistors (MOSFETs) are reported. The addition of edge disorder significantly reduces ON-state currents and increases OFF-state currents, and introduces wide variability across devices. These effects decrease as ribbon widths increase and as edges become smoother. However the bandgap decreases with increasing width, thereby increasing the band-to-band tunneling mediated subthreshold leakage current even with perfect nanoribbons. These results …
In order to continue to improve integrated circuit performance and functionality, scaled transistors with short channel lengths and low thickness are needed. But the further scaling of silicon-based devices and the development of alternative semiconductor channel materials that are compatible with current fabrication processes is challenging. Here we report atomic-layer-deposited indium oxide transistors with channel lengths down to 8 nm, channel thicknesses down to 0.5 nm and equivalent dielectric oxide thickness down to 0.84 nm. Due to the scaled device dimensions and low contact resistance,…
Reverse electrodialysis is a promising method to harvest the osmotic energy stored between seawater and freshwater, but it has been a long-standing challenge to fabricate permselective membranes with the power density surpassing the industry benchmark of 5.0 W $m^{-2}$ for half a century. Herein, we report a vertically-oriented graphene oxide membranes (V-GOMs) with the combination of high ion selectivity and ultrafast ion permeation, whose permeation is three orders of magnitude higher than the extensively studied horizontally stacked GOMs (H-GOMs). By mixing artificial seawater and river wat…
We present a scaling theory of two-dimensional (2D) field effect transistors (FETs). For devices with channel thickness less than 4 nm, the device electrostatics is dominated by the physical gate oxide thickness and not the effective oxide thickness. Specifically, for symmetric double gate (DG) FETs the scale length (Λ) varies linearly with the gate oxide thickness(t_{ox}) as Λ ~ 3/4t_{ox}. The gate oxide dielectric permittivity and the semiconductor channel thickness do not affect the device electrostatics for such device geometries. For an asymmetric device such as single gate (SG) FETs, the…
We report direct measurements of the potential barriers and electronic coupling between nanowire segments within a sketch-based oxide nanotransistor (SketchFET) device. Near room temperature, switching is governed by thermally activation across a potential barrier controlled by the nanowire gate. Below T=150 K, a crossover to quantum field emission is observed that is sensitive to structural phase transitions in the SrTiO3 layer. This direct measurement of the source-drain and gate-drain energy barriers is crucial for the development of room-temperature logic and memory elements and low-temper…
High drive current is a critical performance parameter in semiconductor devices for high-speed, low-power logic applications or high-efficiency, high-power, high-speed radio frequency (RF) analog applications. In this work, we demonstrate an In2O3 transistor grown by atomic layer deposition (ALD) at back-end-of-line (BEOL) compatible temperatures with a record high drain current exceeding 10 A/mm, the performance of which is 2-3 times better than all known transistors with semiconductor channels. A record high transconductance of 4 S/mm is also achieved among all transistors with a planar stru…
In this work, we demonstrate high performance indium-tin-oxide (ITO) transistors with the channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. On-current of 0.243 A/mm is achieved on sub-micron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ωmm and a low contact resistivity of 1.1{\times}10-7 Ωcm2. The ITO transistor with a recessed channel and …
Flexible and transparent electronics presents a new era of electronic technologies. Ubiquitous applications involve wearable electronics, biosensors, flexible transparent displays, radio-frequency identifications (RFIDs), etc.Zinc oxide (ZnO) and related materials are the most commonly used inorganic semiconductors in flexible and transparent devices, owing to their high electrical performance, together with low processing temperature and good optical transparency.In this paper, we review recent advances in flexible and transparent thin-film transistors (TFTs) based on ZnO and related material…
The interface between polar LaAlO3 and non-polar SrTiO3 exhibits a remarkable variety of electronic behavior associated with the formation of an interfacial quasi-two-dimensional electron gas (q-2DEG). By "sketching" patterns of charge on the top LaAlO3 surface, the LaAlO3/SrTiO3 interface conductance can be controlled with near-atomic spatial resolution. Using this technique, a sketch-based oxide nanotransistor (SketchFET) was demonstrated with a minimum feature size of just two nanometers. Here we report direct measurements of the potential barriers and electronic coupling between nanowire s…
Molecular transistors have the potential for switching with lower gate voltages than conventional field-effect transistors. We have calculated the performance of a single-molecule device in which there is interference between electron transport through the highest occupied molecular orbital and the lowest unoccupied molecular orbital of a single molecule. Quantum interference results in a subthreshold slope that is independent of temperature. For realistic parameters the change in gate potential required for a change in source-drain current of two decades is 20 mV, which is a factor of six sma…
A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has been fabricated using silicon-on-insulator metal oxide semiconductor technology. Depending on the back gate polarisation, an electron island is accumulated under the front gate of the device (SET regime), or a field-effect transistor is obtained by pinching off a bottom channel with a negative front gate voltage. The gradual transition between these two cases is observed. This dual function uses both vertical and horizontal tunable potential gradients in non-overlapped silicon-on-insulator…
We present observations of background charge fluctuators near an Al-AlO_x-Al single-electron transistor on an oxidized Si substrate. The transistor design incorporates a heavily doped substrate and top gate, which allow for independent control of the substrate and transistor island potentials. Through controlled charging of the Si/SiO_2 interface we show that the fluctuators cannot reside in the Si layer or in the tunnel barriers. Combined with the large measured signal amplitude, this implies that the defects must be located very near the oxide surface.
We integrate ambipolar quantum dots in silicon fin field-effect transistors using exclusively standard complementary metal-oxide-semiconductor fabrication techniques. We realize ambipolarity by replacing conventional highly-doped source and drain electrodes by a metallic nickel silicide with Fermi level close to the silicon mid-gap position. Such devices operate in a dual mode, either as classical field-effect or single-electron transistor. We implement a classical logic NOT gate at low temperature by tuning two interconnected transistors into opposite polarities. In the quantum regime, we dem…
We incorporate an Al-AlO_x-Al single-electron transistor as the gate of a narrow (~100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET). Near the MOSFET channel conductance threshold, we observe oscillations in the conductance associated with Coulomb blockade in the channel, revealing the formation of a Si single-electron transistor. Abrupt steps present in sweeps of the Al transistor conductance versus gate voltage are correlated with single-electron charging events in the Si transistor, and vice versa. Analysis of these correlations using a simple electrostatic model demonstrat…
We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO$_{4}$ polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale de…
The possible existence of short-channel effects in oxide field-effect transistors is investigated by exploring field-effect transistors with various gate lengths fabricated from LaAlO$_3$-SrTiO$_3$ heterostructures. The studies reveal the existence of channel-length modulation and drain-induced barrier lowering for gate lengths below 1 μm, with a characteristic behavior comparable to semiconducting devices. With the fabrication of field-effect transistors with gate lengths as small as 60 nm the results demonstrate the possibility to fabricate by electron-beam lithography functional devices bas…
Electronic transport in a carbon nanotube (CNT) metal-oxide-semiconductor field effect transistor (MOSFET) is simulated using the non-equilibrium Green's functions method with the account of electron-phonon scattering. For MOSFETs, ambipolar conduction is explained via phonon-assisted band-to-band (Landau-Zener) tunneling. In comparison to the ballistic case, we show that the phonon scattering shifts the onset of ambipolar conduction to more positive gate voltage (thereby increasing the off current). It is found that the subthreshold swing in ambipolar conduction can be made as steep as 40mV/d…
A new method to fabricate non-superconducting mesoscopic tunnel junctions by oxidation of Ti is presented. The fabrication process uses conventional electron beam lithography and shadow deposition through an organic resist mask. Superconductivity in Ti is suppressed by performing the deposition under a suitable background pressure. We demonstrate the method by making a single electron transistor which operated at $T < 0.4$ K and had a moderate charge noise of $2.5 \times 10^{-3}$ e/$\sqrt{\mathrm{Hz}}$ at 10 Hz. Based on nonlinearities in the current-voltage characteristics at higher voltages,…
Two-dimensional (2D) semiconductors are promising channel materials for continued downscaling of complementary metal-oxide-semiconductor (CMOS) logic circuits. However, their full potential continues to be limited by a lack of scalable high-k dielectrics that can achieve atomically smooth interfaces, small equivalent oxide thicknesses (EOT), excellent gate control, and low leakage currents. Here, we report liquid metal printed ultrathin and scalable Ga2O3 dielectric for 2D electronics and electro-optical devices. We directly visualize the atomically smooth Ga2O3/WS2 interfaces enabled by the c…
While decreasing the oxide thickness in carbon nanotube field-effect transistors (CNFETs) improves the turn-on behavior, we demonstrate that this also requires scaling the range of the drain voltage. This scaling is needed to avoid an exponential increase in Off-current with drain voltage, due to modulation of the Schottky barriers at both the source and drain contact. We illustrate this with results for bottom-gated ambipolar CNFETs with oxides of 2 and 5 nm, and give an explicit scaling rule for the drain voltage. Above the drain voltage limit, the Off-current becomes large and has equal ele…
Schottky barrier field-effect transistors (SBFETs) based on few and mono layer phosphorene are simulated by the non-equilibrium Green's function formalism. It is shown that scaling down the gate oxide thickness results in pronounced ambipolar I-V characteristics and significant increase of the minimal leakage current. The problem of leakage is especially severe when the gate insulator is thin and the number of layer is large, but can be effectively suppressed by reducing phosphorene to mono or bilayer. Different from two-dimensional graphene and layered dichalcogenide materials, both the ON-cu…
In this paper, we investigated the performance of thin-film transistors (TFTs) with different channel configurations including single-active-layer (SAL) Sn-Zn-O (TZO), dual-active-layers (DAL) In-Sn-O (ITO)/TZO, and triple-active-layers (TAL) TZO/ITO/TZO. The TAL TFTs were found to combine the advantages of SAL TFTs (a low off-state current) and DAL TFTs (a high mobility and a low threshold voltage). The proposed TAL TFTs exhibit superior electrical performance, e.g. a high on-off state current ratio of 2*10^8, a low threshold voltage of 0.52 V, a high saturation mobility of 145.2 cm2/Vs, and …
Spin-transport characteristics in a Si-based spin metal-oxide-semiconductor field-effect transistor (spin MOSFET): Bias dependence of the spin polarization in Si and magnetoresistance in spin-valve signals
We study the transport properties of deeply scaled monolayer MoS2 n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) using full-band ballistic quantum transport simulations with an atomistic tight-binding Hamiltonian obtained from density functional theory. Our simulations suggest that monolayer MoS2 MOSFETs can provide near-ideal subthreshold slope, and suppression of drain-induced barrier lowering (DIBL) and gate-induced drain leakage (GIDL). However, these full-band simulations also exhibit limited transconductance. These ballistic simulations also exhibit negative diffe…
We describe a planar silicon metal-oxide-semiconductor (MOS) based single hole transistor, which is compatible with conventional Si CMOS fabrication. A multi-layer gate design gives independent control of the carrier density in the dot and reservoirs. Clear Coulomb blockade oscillations are observed, and source-drain biasing measurements show that it is possible to deplete the dot down to the few hole regime, with excited states clearly visible. The architecture is sufficiently versatile that a second hole dot could be induced adjacent to the first one.
We demonstrate non-volatile, n-type, back-gated, MoS$_{2}$ transistors, placed directly on an epitaxial grown, single crystalline, PbZr$_{0.2}$Ti$_{0.8}$O$_{3}$ (PZT) ferroelectric. The transistors show decent ON current (19 $μA/μ$m), high on-off ratio (10$^{7}$), and a subthreshold swing of (SS ~ 92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have selfconsistently confirmed the switching of the ferroelectric and corresponding change in channel cu…
The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of…
We studied transport through ultra-small Si quantum dot transistors fabricated from silicon-on-insulator wafers. At high temperatures, 4K<T<100K, the devices show single-electron or single-hole transport through the lithographically defined dot. At T<4K, current through the devices is characterized by multidot transport. From the analysis of the transport in samples with double-dot characteristics, we conclude that extra dots are formed inside the thermally grown gate oxide which surrounds the lithographically defined dot.
Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are of potential to use in non-volatile memory technology, but suffer from short retention times, which limits their wider application. Here we report a ferroelectric semiconductor field-effect transistor in which a two-dimensional ferroelectric semiconductor, indium selenide (α-In2Se3), is used as the channel material in the device. α-In2Se3 was chosen due to its appropriate bandgap, ro…
A simple and highly reproducible single electron transistor (SET) has been fabricated using gated silicon nanowires. The structure is a metal-oxide-semiconductor field-effect transistor made on silicon-on-insulator thin films. The channel of the transistor is the Coulomb island at low temperature. Two silicon nitride spacers deposited on each side of the gate create a modulation of doping along the nanowire that creates tunnel barriers. Such barriers are fixed and controlled, like in metallic SETs. The period of the Coulomb oscillations is set by the gate capacitance of the transistor and ther…
