We report record performance for black phosphorus p-MOSFETs. The devices have locally patterned back gates and 20-nm-thick HfO2 gate dielectrics. Devices with effective gate length, Leff = 1.0 um display extrinsic transconductance, gm, of 101 uS/um at a drain-to-source bias voltage, Vds = -3 V. Temperature-dependent analysis also shows that the subthreshold slope, SS, is nearly ideal, with a minimum value of SS = 66 mV/decade at room temperature and Vds = -0.1 V. Furthermore, devices with 7-nm HfO2 dielectrics and Leff = 0.3 um displayed gm as high as 204 uS/um at Vds = -1.5 V.
Ambipolar black phosphorus MOSFETs with record n-channel extrinsic transconductance are reported. The devices consist of multi-layer black phosphorus aligned to a local back-gate electrode with 10-nm-thick HfO2 gate dielectric. Before passivation, devices with 0.3-um gate length behaved as p-MOSFETs with peak extrinsic transconductance, gm, of 282 uS/um at VDS = -2 V. After passivation, the same devices displayed ambipolar behavior, and when tested as n-MOSFETs, had peak gm = 66 uS/um at VDS = +2 V, and similar devices on the same wafer had gm as high as 80 uS/um. These results are an importan…
In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) = \ln10~k_BT/e$. However, recent low-temperature studies of different advanced CMOS technologies have reported $SS$(4K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of $SS(T)$ in 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxi…
This letter reports a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures. Below a critical temperature, the derived limit saturates to a value that is independent of temperature and proportional to the extent of a band tail. Since the saturation is universally observed in different types of MOSFETs (regardless of dimension or semiconductor material), the band tail is attributed to the finite periodicity of the lattice in a semiconductor volume, and to a lesser extent to additional lattice perturbations such as…
In this paper, we present the unique features exhibited by modified asymmetrical Double Gate (DG) silicon on insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, Dual Material Double Gate (DMDG) SOI MOSFET, exhibits significantly reduced short channel effects when compared with the DG SOI MOSFET. Short channel effects in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, e…
Ideal, completely coherent quantum transport calculations had predicted that superlattice MOSFETs may offer steep subthreshold swing performance below 60mV/dec to around 39mV/dec. However, the high carrier density in the superlattice source suggest that scattering may significantly degrade the ideal device performance. Such effects of electron scattering and decoherence in the contacts of superlattice MOSFETs are examined through a multiscale quantum transport model developed in NEMO5. This model couples NEGF-based quantum ballistic transport in the channel to a quantum mechanical density of s…
We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily-doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4,000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate ox…
High performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (Lch) down to 20nm have been fabricated by integrating a higher-k LaAlO3-based gate stack with an equivalent oxide thickness of 1.2nm. It is found that inserting an ultrathin (0.5nm) Al2O3 interfacial layer between higher-k and InGaAs can significantly improve the interface quality and reduce device variation. As a result, a record low subthreshold swing of 63mV/dec has been demonstrated at sub-80nm Lch for the first time, making InGaAs GAA nanowire devices a strong candidate for future low-power transistors.
Ambipolar currents in Germanium p-type nanowire Schottky barrier MOSFETs were calculated fully quantum-mechanically by using the multi-band k.p method and the non-equilibrium Green's function approach. We investigated the performance of devices with 100, 110, and 111 channel orientations, respectively, by varying the nanowire width, Schottky barrier height, and EOT. The 111 oriented devices showed the best performance. In comparison to Si as a channel material, Ge is more desirable because more current can be injected into the channel, resulting in steeper subthreshold slope and higher on-stat…
InGaAs gate-all-around nanowire MOSFETs with channel length down to 50nm have been experimentally demonstrated by top-down approach. The nanowire size-dependent transport properties have been systematically investigated. It is found that reducing nanowire dimension leads to higher on-current, transconductance and effective mobility due to stronger quantum confinement and the volume inversion effect. TCAD quantum mechanical simulation has been carried out to study the inversion charge distribution inside the nanowires. Volume inversion effect appears at a larger dimension for InGaAs nanowire MO…
In this work, we present a computational study on the possibility of strain engineering in monolayer Black Phosphorus (black P) and Blue Phosphorus (blue P) based MOSFETs. The material properties like band structure, carrier effective masses, carrier densities at band extrema are evaluated using Generalized Gradient Approximation (GGA) in Density Functional Theory (DFT).Thereafter self-consistent Non-Equilibrium Greens Function (NEGF) simulations are carried out to study the device performance metrics (such as output characteristics, ON currents, transconductance etc.) of such strained black P…
A MOSFET threshold voltage extraction method covering the entire range of drain-to-source voltage, from linear to saturation modes, is presented. Transconductance-to-current ratio is obtained from MOSFET transfer characteristics measured at low to high drain voltage. Based on the charge-based modeling approach, a near-constant value of threshold voltage is obtained over the whole range of drain voltage for ideal, long-channel MOSFETs. The method reveals a distinct increase of threshold voltage versus drain voltage for halo-implanted MOSFETs in the low drain voltage range. The method benefits f…
A real-space quantum transport simulator for carbon nanoribbon (CNR) MOSFETs has been developed. Using this simulator, the performance of carbon nanoribbon (CNR) MOSFETs is examined in the ballistic limit. The impact of quantum effects on device performance of CNR MOSFETs is also studied. We found that 2D semi-infinite graphene contacts provide metal-induced-gap-states (MIGS) in the CNR channel. These states would provide quantum tunneling in the short channel device and cause Fermi level pining. These effects cause device performance degradation both on the ON-state and the OFF-state. Pure 1D…
We investigate the design of steep-slope metal-oxide-semiconductor field-effect transistors (MOSFETs) exploiting monolayers of transition metal dihalides as channel materials. With respect to other previously proposed steep-slope transistors, these devices require simplified manufacturing processes, as no confinement of the 2D material is needed, nor any tunneling heterojunction or ferroelectric gate insulators, and only n- or p-type contacts are demanded. We demonstrate their operation by studying an implementation based on monolayer CrI$_2$ through quantum transport simulations. We show that…
In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-\k{appa} gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating voltage of 0.5 V. Using calibrated two-dimensional simulations it is shown that even for such a low operating voltage, the gate leakage substantially degrades several subthreshold parameters of the TFET such as the off-state current, minimum subthreshold swing and average subthreshold swing. While the drain-offset as well as the short-gate are effective methods…
Tunneling field-effect transistors (TFETs) have gained a great deal of recent interest due to their potential to reduce power dissipation in integrated circuits. One major challenge for TFETs so far has been achieving high drive currents, which is a prerequisite for high-performance operation. In this paper we explore the performance potential of a 1D TFET with a broken-gap heterojunction source injector using dissipative quantum transport simulations based on the nonequilibrium Green's function formalism, and the carbon nanotube bandstructure as the model 1D material system. We provide detail…
The operation of an integrated two-dimensional complementary metal-oxide-semiconductor inverter with well-matched input/output voltages is reported. The circuit combines a few-layer MoS2 n-MOSFET and a black phosphorus (BP) p-MOSFET fabricated using a common local backgate electrode with thin (20 nm) HfO2 gate dielectric. The constituent devices have linear threshold voltages of -0.8 V and +0.8 V and produce peak transconductances of 16 uS/um and 41 uS/um for the MoS2 n-MOSFET and BP p-MOSFET, respectively. The inverter shows a voltage gain of 3.5 at a supply voltage, VDD = 2.5 V, and has peak…
Two-dimensional (2D) semiconductors have attracted tremendous interests as natural passivation and atomically thin channels that could facilitate continued transistor scaling. However, air-stable 2D semiconductors with high performance were quite elusive. Recently, extremely air-stable MoSi2N4 monolayer had been successfully fabricated [Hong et al., Science 369, 670 (2020)]. To further reveal its potential applications in the sub-5 nm MOSFETs, there is an urgent need to develop integrated circuits. Here we report first-principles quantum transport simulations on the performance limits of n- an…
We analyze the distributions of electric potential and field, polarization and charge, and the differential capacitance of a silicon metal-oxide-ferroelectric field effect transistor (MOSFET), in which a gate insulator consists of thin layers of dielectric SiO2 and weak ferroelectric HfO2. It appeared possible to achieve a quasi-steady-state negative capacitance of the HfO2 layer, C_(HfO_2 )<0, if the layer thickness is close to the critical thickness of the size-induced ferroelectric-paraelectric phase transition. The quasi-steady-state negative capacitance, being a very slow-varying transien…
High performance enhancement mode semiconducting carbon nanotube field-effect transistors (CNTFETs) are obtained by combining ohmic metal-tube contacts, high dielectric constant HfO2 films as gate insulators, and electrostatically doped nanotube segments as source/drain electrodes. The combination of these elements affords high ON currents, subthreshold swings of ~ 70-80 mV/decade, and allows for low OFF currents and suppressed ambipolar conduction. The doped source and drain approach resembles that of MOSFETs and can impart excellent OFF states to nanotube FETs under aggressive vertical scali…
The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of…
The availability of transistors capable of operating at low supply voltage is essential to improve the key performance metric of computing circuits, i.e., the number of operations per unit energy. In this paper, we propose a new device concept for energy-efficient, steep-slope transistors based on heterojunctions of 2D materials. We show that by injecting electrons from an isolated and weakly dispersive band into a strongly dispersive one, subthermionic subthreshold swings can be obtained, as a result of a cold-source effect and of a reduced thermalization of carriers. This mechanism is implem…
In this work, using 3D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the on-off ratio as well as the subthreshold characteristics in an ultra-short channel n-type device without significant on performance degradation. We also show that the underlap knob can be tuned to mitigate the device quality degradation in presence of interface traps. The obtained results are shown to be very promising when compared against ITRS 2009 performance p…
Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ra…
In this study, InSb nanowires have been formed by electrodeposition and integrated into NW-FETs. NWs were formed in porous anodic alumina (PAA) templates, with the PAA pore diameter of approximately 100 nm defining the NW diameter. Following annealing at 125C and 420C respectively, the nanowires exhibited the zinc blende crystalline structure of InSb, as confirmed from x-ray diffraction and high resolution transmission electron microscopy. The annealed nanowires were used to fabricate nanowire field effect transistors (NW-FET) each containing a single NW with 500 nm channel length and gating t…
