Fault-tolerant routing (FTR) in Networks-on-Chip (NoCs) has become a common practice to sustain the performance of multi-core systems with an increasing number of faults on a chip. On the other hand, usage of third-party intellectual property blocks has made security a primary concern in modern day designs. This article presents a mechanism to mitigate a denial-of-service attack, namely packet drop attack, which may arise due to the hardware Trojans (HTs) in NoCs that adopt FTR algorithms. HTs, associated with external kill switches, are conditionally triggered to enable the attack scenario. Security modules, such as authentication unit, buffer shuffler, and control unit, have been proposed to thwart the attack in runtime and restore secure packet flow in the NoC. These units work together as a shield to safeguard the packets from proceeding towards the output ports with faulty links. Synthesis results show that the proposed secure FT router, when compared with a baseline FT router, has area and power overheads of at most 4.04% and 0.90%, respectively. Performance evaluation shows that SeFaR has acceptable overheads in the execution time, energy consumption, average packet latency, and power-latency product metrics when compared with a baseline FT router while running real benchmarks, as well as synthetic traffic. Further, a possible design of a comprehensive secure router has been presented with a view to addressing and mitigating multiple attacks that can arise in the NoC routers.
DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
为了阐明RowHammer如何在电路级影响现代和未来的设备，我们首先在1580 DRAM芯片上对RowHammer进行了实验表征（408个DDR3、652个DDR4和520个LPDDR4），来自300个DRAM模块（60 x DDR3、110 x DDR4和130 x LPDDR4），禁用RowHammer保护机制，跨越三大DRAM制造商的多个不同技术节点。我们的研究明确表明，较新的DRAM芯片更容易受到RowHammer的影响：随着设备特征尺寸的减小，引发RowHammer位翻转所需的激活次数也减少了，在我们测试的最脆弱的芯片中，激活次数减少到9.6k（每行4.8k到两行）。我们评估了五个国家的最先进的RowHammer缓解机制，使用周期准确的模拟的背景下，从我们的芯片采取的真实数据，研究如何缓解机制的规模与芯片的脆弱性。我们发现，现有的机制要么是不可扩展的，或遭受过大的性能开销，在预计未来的设备，我们观察到的趋势RowHammer漏洞。因此，研究更有效的RowHammer解决方案至关重要。
An Emerging NVM-Based On-Chip Training Architecture with Non-Ideality Mitigation Through Bipolar Weight Distributions
State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所处理器重点实验室）；University of Chinese Academy of Sciences（中国科学院大学）；Southern University of Science and Technology（南方科技大学）；Pengcheng Laboratory（鹏城实验室）
Evaluating Built-in ECC of FPGA on-chip Memories for the Mitigation of Undervolting Faults
Barcelona Supercomputing Center (BSC)（巴塞罗那超级计算中心）；IIIA - Artificial Intelligence Research Institute CSIC - Spanish National Research Council（西班牙国家研究委员会IIIA人工智能研究所）；Georgia Institute of Technology（佐治亚理工学院）；Twentieth Century Fox（二十世纪福克斯公司）；Starfleet Academy（星际舰队学院）
FT-Pilot: Automated Fault-Tolerant RTL Rewriting via Vulnerability-Guided LLMs
University of Chinese Academy of Sciences（中国科学院大学）；State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所处理器与存储系统国家重点实验室）；CASTEST Co., Ltd.（北京芯测科技有限公司）；Bodesi Technologies（博德思科技）
AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM
School of Integrated Circuits（集成电路学院）；Peking University（北京大学）；Beijing Advanced Innovation Center for Integrated Circuits（北京集成电路先进创新中心）；Southeast University（东南大学）；School of Computer Science（计算机科学学院）
Cross-Layer Optimization for Fault-Tolerant Deep Learning
Institute of Computing Technology, Chinese Academy of Sciences（中国科学院计算技术研究所）；University of Chinese Academy of Sciences（中国科学院大学）；Beijing Institute of Control Engineering（北京控制工程研究所）
