AIM：面向高性能存内计算架构级IR-drop缓解的软件与硬件协同设计
AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM
AI总结：
本文提出AIM软硬件协同设计框架，通过建立PIM工作负载与IR-drop的关联、软件优化、动态V-f调节及HR感知任务映射，在7nm 256-TOPS PIM芯片上实现69.2%的IR-drop缓解、2.29倍能效提升和1.152倍加速。
摘要：
SRAM存内计算（PIM）已成为高性能存内计算最有前景的实现方式，具有卓越的计算密度、能效和计算精度。然而，追求更高性能需要更复杂的电路设计和更高的工作频率，这加剧了IR-drop问题。严重的IR-drop会显著降低芯片性能，甚至威胁可靠性。传统的电路级IR-drop缓解方法（如后端优化）资源密集，且往往牺牲功耗、性能和面积（PPA）。为应对这些挑战，我们提出AIM，一种面向高性能PIM架构级IR-drop缓解的全面软件与硬件协同设计。首先，利用PIM的位串行和原位数据流处理特性，我们引入Rtog和HR，在PIM工作负载与IR-drop之间建立直接关联。在此基础上，我们提出LHR和WDS，通过软件优化在保持计算精度的同时，实现架构级IR-drop缓解的广泛探索。随后，我们开发IR-Booster，一种动态调节机制，将软件级HR信息与基于硬件的IR-drop监测相结合，自适应调整PIM宏单元的V-f对，从而实现更高的能效和性能。最后，我们提出HR感知的任务映射方法，桥接软件与硬件设计以实现最优改进。在7nm 256-TOPS PIM芯片上的布局后仿真结果表明，AIM实现了高达69.2%的IR-drop缓解，带来2.29倍的能效提升和1.152倍的加速。
英文摘要：
SRAM Processing-in-Memory (PIM) has emerged as the most promising implementation for high-performance PIM, delivering superior computing density, energy efficiency, and computational precision. However, the pursuit of higher performance necessitates more complex circuit designs and increased operating frequencies, which exacerbate IR-drop issues. Severe IR-drop can significantly degrade chip performance and even threaten reliability. Conventional circuit-level IR-drop mitigation methods, such as back-end optimizations, are resource-intensive and often compromise power, performance, and area (PPA). To address these challenges, we propose AIM, comprehensive software and hardware co-design for architecture-level IR-drop mitigation in high-performance PIM. Initially, leveraging the bit-serial and in-situ dataflow processing properties of PIM, we introduce Rtog and HR, which establish a direct correlation between PIM workloads and IR-drop. Building on this foundation, we propose LHR and WDS, enabling extensive exploration of architecture-level IR-drop mitigation while maintaining computational accuracy through software optimization. Subsequently, we develop IR-Booster, a dynamic adjustment mechanism that integrates software-level HR information with hardware-based IR-drop monitoring to adapt the V-f pairs of the PIM macro, achieving enhanced energy efficiency and performance. Finally, we propose the HR-aware task mapping method, bridging software and hardware designs to achieve optimal improvement. Post-layout simulation results on a 7nm 256-TOPS PIM chip demonstrate that AIM achieves up to 69.2% IR-drop mitigation, resulting in 2.29x energy efficiency improvement and 1.152x speedup.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
