基于DRAM的计算内/近内存方法的供电方面比较研究
A comparative study on power delivery aspects of compute-in/near-memory approaches using DRAM
AI总结：
本文综述了DRAM基计算内/近内存系统的供电网络挑战，提出了一个统一分类法，并分析了代表性技术对供电网络的影响及缓解策略。
摘要：
内存计算（PIM）通过在内存内部执行计算来缓解内存墙问题，减少数据移动并提高能效。基于DRAM的PIM因其高密度、成熟的制造生态系统以及与现有系统的兼容性而特别有吸引力。最近的工作利用了DRAM层次结构的多个级别——包括子阵列、存储体和3D堆叠组织——通过多行激活、行缓冲操作和近存储体计算单元等机制实现内存计算。然而，这些方法引入了非传统的电流需求模式，给供电网络（PDN）带来了挑战。本文调查了基于DRAM的PIM系统中的PDN挑战，并提出了一个统一的分类法，该分类法沿时间（突发与持续）和空间（局部与分布）维度表征了PIM引起的电流行为。利用这一框架，我们分析了代表性PIM技术如何通过突发激活、多行并发和大规模并行执行对PDN造成压力，导致电压跌落、IR压降和热热点。我们进一步讨论了利用现有架构和电路级机制（包括时序约束、内存控制器调度、数据放置以及存储体和库级电源管理）的DRAM特定缓解策略。本调查强调了PDN感知设计对于可扩展且可靠的基于DRAM的PIM系统的重要性，并概述了关键的未来研究方向。
英文摘要：
Compute-in-memory (PIM) mitigates the memory wall by performing computation within memory, reducing data movement and improving energy efficiency. DRAM-based PIM is particularly attractive due to its high density, mature manufacturing ecosystem, and compatibility with existing systems. Recent works exploit multiple levels of the DRAM hierarchy - including subarrays, banks, and 3D-stacked organizations - to enable in-memory computation using mechanisms such as multi-row activation, row-buffer operations, and near-bank compute units. However, these approaches introduce non-traditional current demand patterns that challenge the power delivery network (PDN). This paper surveys PDN challenges in DRAM-based PIM systems and proposes a unified taxonomy that characterizes PIM-induced current behavior along temporal (burst vs. sustained) and spatial (localized vs. distributed) dimensions. Using this framework, we analyze how representative PIM techniques stress the PDN through bursty activations, multi-row concurrency, and large-scale parallel execution, leading to voltage droop, IR drop, and thermal hotspots. We further discuss DRAM-specific mitigation strategies leveraging existing architectural and circuit-level mechanisms, including timing constraints, memory controller scheduling, data placement, and bank- and vault-level power management. This survey highlights the importance of PDN-aware design for scalable and reliable DRAM-based PIM systems and outlines key future research directions.
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