基于TSV的功率传输网络使能的3D堆叠DRAM中电迁移效应的表征和减轻
Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs
摘要：
随着3D堆叠DRAM架构变得越来越普遍，找到表征和减轻可能阻碍其固有访问并行性和吞吐量的不利影响的方法变得重要。这种不利因素的一个示例是3D堆叠DRAM架构的功率输送网络（PDN）的硅通孔（TSV）中的电迁移（EM）效应。若干现有工作已经解决了3D集成电路的TSV中的EM效应。然而，没有先前的工作已经解决了在PDN TSV中的EM对3D堆叠DRAM的性能和寿命的影响。在本文中，我们的特点的EM在PDN TSV的混合存储器立方体（HMC）架构采用传统的PDN设计与电源和接地TSV的集群布局的影响。然后，我们提出了一种新的PDN设计与分布式布局的电源和接地TSV，并表明它可以减轻EM对HMC架构性能的不利影响，而不需要额外的电源和接地引脚。我们的基准驱动的基于仿真的分析表明，相比集群PDN布局，我们提出的分布式PDN布局提高了EM影响的HMC架构的寿命长达10年。在这个有用的寿命期间，HMC架构产生高达1.51倍的能量延迟积（EDP）。
英文摘要：
With 3D-stacked DRAM architectures becoming more prevalent, it has become important to find ways to characterize and mitigate the adverse effects that can hinder their inherent access parallelism and throughput. One example of such adversities is the electromigration (EM) effects in the through-silicon vias (TSVs) of the power delivery network (PDN) of 3D-stacked DRAM architectures. Several prior works have addressed the effects of EM in TSVs of 3D integrated circuits. However, no prior work has addressed the effects of EM in the PDN TSVs on the performance and lifetime of 3D-stacked DRAMs. In this paper, we characterize the effects of EM in PDN TSVs on a Hybrid Memory Cube (HMC) architecture employing the conventional PDN design with clustered layout of power and ground TSVs. We then present a new PDN design with a distributed layout of power and ground TSVs and show that it can mitigate the adverse effects of EM on the HMC architecture performance without requiring additional power and ground pins. Our benchmark-driven simulation-based analysis shows that compared to the clustered PDN layout, our proposed distributed PDN layout improves the EM-affected lifetime of the HMC architecture by up to 10 years. During this useful lifetime, the HMC architecture yields up to 1.51 times less energy-delay product (EDP).
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
