纳米VLSI中的光刻热点检测和缓解
Lithography Hotspot Detection and Mitigation in Nanometer VLSI
摘要：
随着持续的特征尺寸缩放，即使是最先进的半导体制造工艺也常常会遇到具有较差的可印刷性和良率的布局。识别光刻热点在物理验证和早期物理设计阶段都很重要。虽然详细的光刻模拟可以非常准确，但对于全芯片规模和物理设计内环来说，它们可能在计算上过于昂贵。同时，基于模式匹配和机器学习的热点检测方法可以为全芯片级物理验证和设计提供可接受的质量和快速的周转时间。在本文中，我们讨论了一些关键问题和最近的结果，光刻热点检测和减轻纳米超大规模集成电路。
英文摘要：
With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithography hotspots is important at both physical verification and early physical design stages. While detailed lithography simulations can be very accurate, they may be too computationally expensive for full-chip scale and physical design inner loops. Meanwhile, pattern matching and machine learning based hotspot detection methods can provide acceptable quality and yet fast turn-around-time for full-chip scale physical verification and design. In this paper, we discuss some key issues and recent results on lithography hotspot detection and mitigation in nanometer VLSI.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
