具有互连串扰的容错计算新范例
A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks
摘要：
先进技术节点处的CMOS集成芯片变得更容易受到各种故障源的影响，如制造不精确、变化、老化等。高功率微波、网络安全威胁等）和环境影响（即，辐射）也对集成电路造成可靠性威胁。传统的基于硬件冗余的技术，如三模冗余（TMR），四重（QL）逻辑等，虽然在一定程度上减轻了风险，但它们增加了巨大的硬件开销，并且不是很有效。固有地能够在有限的占用空间中实现多个功能的真正的多态电路可以以有限的开销增强电路的容错性/恢复。我们展示了一种新的串扰逻辑为基础的多态电路的方法来实现紧凑和高效的故障恢复电路。我们展示了一系列的多态原语门和它们在功能单元中的使用。功能单元是一个单一的算术电路，能够根据控制输入提供乘法/排序/加法输出。在ALU中使用这种多态计算单元将意味着即使当ALU的2/3损坏时，功能输出的正确路径也是可能的。我们的比较结果与现有的多态技术和CMOS显示28%和62%的晶体管数量减少，分别为相同的功能。结合故障检测算法，所提出的多态电路概念可以是具有最小开销的容错电路设计方向的变革。
英文摘要：
The CMOS integrated chips at advanced technology nodes are becoming more vulnerable to various sources of faults like manufacturing imprecisions, variations, aging, etc. Additionally, the intentional fault attacks (e.g., high power microwave, cybersecurity threats, etc.) and environmental effects (i.e., radiation) also pose reliability threats to integrated circuits. Though the traditional hardware redundancy-based techniques like Triple Modular Redundancy (TMR), Quadded (QL) Logic etc. mitigate the risk to some extent, they add huge hardware overhead and are not very effective. Truly polymorphic circuits that are inherently capable of achieving multiple functionalities in a limited footprint could enhance the faultresilience/recovery of the circuits with limited overhead. We demonstrate a novel crosstalk logic based polymorphic circuit approach to achieve compact and efficient fault resilient circuits. We show a range of polymorphic primitive gates and their usage in a functional unit. The functional unit is a single arithmetic circuit that is capable of delivering Multiplication/Sorting/Addition output depending on the control inputs. Using such polymorphic computing units in an ALU would imply that a correct path for functional output is possible even when 2/3rd of the ALU is damaged. Our comparison results with respect to existing polymorphic techniques and CMOS reveal 28% and 62% reduction in transistor count respectively for the same functionalities. In conjunction with fault detection algorithms, the proposed polymorphic circuit concept can be transformative for fault tolerant circuit design directions with minimum overhead.
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