RC耦合互连线时延解析模型的改进
Improved Analytical Delay Models for RC-Coupled Interconnects
摘要：
随着工艺技术向深亚微米发展，串扰延迟问题变得越来越严重，尤其是对于全局片上总线。为了解决这个问题，需要精确的耦合互连线的延迟模型。特别地，基于分析方法的延迟模型是期望的，因为它们不仅对技术在很大程度上是透明的，而且明确地建立耦合互连的延迟与过渡模式之间的连接，从而实现串扰缓解技术，诸如串扰避免码（CAC）。不幸的是，现有的分析延迟模型，如[1]中广泛引用的模型，具有有限的准确性，并且没有考虑负载电容。在本文中，我们提出了分析延迟耦合互连模型，解决这些缺点。通过考虑更多的线和避免Elmore延迟，我们的延迟模型比[1]中的模型实现了更好的准确性。
英文摘要：
As the process technologies scale into deep submicron region, crosstalk delay is becoming increasingly severe, especially for global on-chip buses. To cope with this problem, accurate delay models of coupled interconnects are needed. In particular, delay models based on analytical approaches are desirable, because they not only are largely transparent to technology, but also explicitly establish the connections between delays of coupled interconnects and transition patterns, thereby enabling crosstalk alleviating techniques such as crosstalk avoidance codes (CACs). Unfortunately, existing analytical delay models, such as the widely cited model in [1], have limited accuracy and do not account for loading capacitance. In this paper, we propose analytical delay models for coupled interconnects that address these disadvantages. By accounting for more wires and eschewing the Elmore delay, our delay models achieve better accuracy than the model in [1].
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
