GRACIDIT：用于Zynq UltraScale+ FPGA中配置诱导路由延迟预测的图-电路数字孪生
GRACIDIT: Graph-Circuit Digital Twin for Configuration-Induced Routing Delay Prediction in Zynq UltraScale+ FPGAs
- Department of Electrical Engineering, École de technologie supérieure (ÉTS)（高等电力技术学院）
机构由 AI 辅助整理，请以论文原文为准。
AI总结：
提出GRACIDIT数字孪生框架，结合路由图特征与降阶电学模型，预测Zynq UltraScale+ FPGA中配置诱导的路由延迟，误差7.8皮秒，召回率87.4%。
AI中文摘要：
基于SRAM的FPGA中，配置诱导的扰动可能激活休眠的可编程路由分支，并在不立即产生功能错误的情况下增加路径延迟。尽管先前的研究已分别探讨了这些延迟变化的电学起源、其原位检测以及商用路由架构的拓扑结构，但一种能够在可编程互连点和路由网线粒度上预测其时序影响的可扩展方法仍然缺失。本文提出GRACIDIT，一个用于预测Zynq UltraScale+ FPGA中配置诱导路由延迟退化的图-电路数字孪生框架。该框架从厂商设计数据库中提取XCZU7EV可编程架构的路由资源图，识别与活跃路由相邻的未激活可编程互连点，并通过其分支拓扑、几何跨度、扇出、物理区域和下游负载来表示每个候选扰动。这些图特征与校准的降阶电学模型相结合，以估计由单次和累积路由分支激活引入的延迟。在ZCU104平台上生成受控的配置等效扰动，并使用互补的路由域振荡器和相位扫描探针进行表征。所得模型将预测的延迟偏移与可用的时序裕量相关联，以对易受攻击的可编程互连点和路由网线进行排序，并构建可编程架构的空间脆弱性图谱。实验评估表明，平均绝对预测误差为7.8皮秒，对违反时序裕量的扰动实现了87.4%的召回率，并对最易受攻击的路由资源达到了0.90的Recall at 10值。
英文摘要：
Configuration-induced perturbations in SRAM-based FPGAs may activate dormant programmable routing branches and increase path delay without immediately producing a functional error. Although prior studies have separately investigated the electrical origin of these delay changes, their in-situ detection, and the topology of commercial routing fabrics, a scalable method for predicting their timing impact at the granularity of programmable interconnect points and routed nets remains unavailable. This paper presents GRACIDIT, a graph-circuit digital twin framework for predicting configuration-induced routing delay degradation in Zynq UltraScale+ FPGAs. The proposed framework extracts the routing-resource graph of the XCZU7EV programmable fabric from the vendor design database, identifies inactive programmable interconnect points adjacent to active routes, and represents each candidate perturbation through its branch topology, geometric span, fan-out, physical region, and downstream loading. These graph features are combined with a calibrated reduced-order electrical model to estimate the delay introduced by single and cumulative routing-branch activations. Controlled configuration-equivalent perturbations are generated on a ZCU104 platform and characterized using complementary routing-domain oscillators and phase-sweep probes. The resulting model associates predicted delay shifts with available timing slack to rank vulnerable programmable interconnect points and routed nets and to construct a spatial vulnerability atlas of the programmable fabric. Experimental evaluation demonstrates a mean absolute prediction error of 7.8 ps, achieves 87.4 percent recall for slack-violating perturbations, and attains a Recall at 10 value of 0.90 for the most vulnerable routing resources.
