Increasing storage density exacerbates DRAM read disturbance, a circuit-level vulnerability exploited by system-level attacks. Unfortunately, existing defenses are either ineffective or prohibitively expensive. Efficient mitigation is critical to ensure robust (reliable, secure, and safe) execution in future DRAM-based systems. This dissertation tackles two problems: 1) protecting DRAM-based systems becomes more expensive as technology scaling increases read disturbance vulnerability, and 2) many existing solutions depend on proprietary knowledge of DRAM internals. First, we build a detailed understanding of DRAM read disturbance by rigorously characterizing off-the-shelf modern DRAM chips under varying 1) temperatures, 2) memory access patterns, 3) in-chip locations, and 4) voltage. Our novel observations demystify the implications of large DRAM read disturbance variation on future DRAM read disturbance attacks and solutions. Second, we propose new mechanisms that mitigate read disturbance bitflips efficiently and scalably by leveraging insights into DRAM chip design: 1) subarray-level parallelism and 2) variation in read disturbance across DRAM rows in off-the-shelf DRAM chips. Third, we propose a novel solution that mitigates DRAM read disturbance by selectively throttling unsafe memory accesses that might otherwise cause read disturbance bitflips without proprietary knowledge of DRAM chip internals. We demonstrate that it is possible to mitigate DRAM read disturbance efficiently and scalably with worsening DRAM read disturbance by 1) building a detailed understanding of DRAM read disturbance, 2) leveraging insights into DRAM chips, and 3) devising novel solutions that do not require proprietary knowledge of DRAM chip internals. Our experimental insights and solutions enable future works targeting robust memory systems.
Demystifying DRAM Read Disturbance: Bridging the Gap Between Experimental Characterization and Device-Level Modeling of RowHammer and RowPress Phenomena
ETH Zurich（苏黎世联邦理工学院）；East China Normal University（华东师范大学）；Shanghai Jiao Tong University（上海交通大学）
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques
为了阐明RowHammer如何在电路级影响现代和未来的设备，我们首先在1580 DRAM芯片上对RowHammer进行了实验表征（408个DDR3、652个DDR4和520个LPDDR4），来自300个DRAM模块（60 x DDR3、110 x DDR4和130 x LPDDR4），禁用RowHammer保护机制，跨越三大DRAM制造商的多个不同技术节点。我们的研究明确表明，较新的DRAM芯片更容易受到RowHammer的影响：随着设备特征尺寸的减小，引发RowHammer位翻转所需的激活次数也减少了，在我们测试的最脆弱的芯片中，激活次数减少到9.6k（每行4.8k到两行）。我们评估了五个国家的最先进的RowHammer缓解机制，使用周期准确的模拟的背景下，从我们的芯片采取的真实数据，研究如何缓解机制的规模与芯片的脆弱性。我们发现，现有的机制要么是不可扩展的，或遭受过大的性能开销，在预计未来的设备，我们观察到的趋势RowHammer漏洞。因此，研究更有效的RowHammer解决方案至关重要。
University of Sussex（萨塞克斯大学）；Montanarius Ltd（Montanarius 有限公司）；Royal Holloway University of London（伦敦大学皇家霍洛威学院）；Huawei 2012 Labs, Huawei R&D UK（华为2012实验室，华为英国研发中心）；Arm Ltd（安谋国际科技股份有限公司）；University College London（伦敦大学学院）
