AI 中文总结
本研究弥合了RowHammer与RowPress的实验表征与器件级建模的差距，通过TCAD仿真更新了器件级错误机制，为DRAM读干扰的表征与缓解提供了基础。
AI 中文摘要
DRAM读干扰（如RowHammer和RowPress）是一类关键的鲁棒性问题，访问DRAM时可能在其他未访问的DRAM位置引发意外的位翻转。DRAM读干扰位翻转会严重影响基于DRAM的计算系统的安全、可靠运行。许多前期工作对这些位翻转进行了实验表征，并基于经验结果提出了缓解措施；另有一些器件级工作研究了其潜在物理机制，但这些机制无法完全解释所有主要的实验观测结果。本研究旨在弥合RowHammer与RowPress的实验表征与器件级建模及理解之间的差距，为后续理解、表征和缓解DRAM读干扰的研究提供原则性基础。首先，我们识别并验证了现有器件级模型所描述的RowHammer与RowPress物理机制，与其位翻转实验表征之间存在的差距和不一致性，聚焦于三个应与一阶物理机制对应的基本指标：1）位翻转方向；2）位翻转数量；3）触发首次位翻转所需的最少激活行数量（即ACmin）。其次，我们开展了一套全面且严谨的TCAD仿真，该仿真结果与RowHammer和RowPress位翻转的实验表征中观测到的现象相匹配。基于仿真结果，我们1）总结了用于理解RowHammer与RowPress位翻转的更新后的器件级错误机制；2）确定了对仿真结果是否与真实芯片表征匹配具有显著影响的关键建模与仿真参数。我们还讨论了上述发现对两方面的意义：1）DRAM读干扰位翻转的严谨、全面且高效的实验表征方法；2）DRAM读干扰缓解技术的设计。
英文摘要
DRAM read disturbance, like RowHammer and RowPress, is a critical robustness issue where accessing DRAM can cause unintended bitflips in other unaccessed DRAM locations. DRAM read disturbance bitflips significantly impact the safe, secure, and reliable operation of DRAM-based computing systems. Many prior works experimentally characterize these bitflips and propose mitigations based on empirical results. Other device-level works study their underlying physical mechanisms, but these mechanisms do not fully explain all major empirical observations. Our goal is to bridge the gap between experimental characterization and device-level modeling and understanding of RowHammer and RowPress, providing a principled foundation for future work on understanding, characterizing, and mitigating DRAM read disturbance. We first identify and demonstrate gaps and inconsistencies between the physical mechanisms of RowHammer and RowPress described by existing device-level models and experimental characterization of their bitflips. We focus on three fundamental metrics that should map to first-order physical mechanisms: 1) bitflip directions, 2) bitflip counts, and 3) the minimum number of aggressor row activations that trigger the first bitflips (i.e., ACmin). Second, we present a comprehensive and rigorous set of TCAD simulations that match phenomena observed in experimental characterizations of RowHammer and RowPress bitflips. From our results, we 1) summarize updated device-level error mechanisms for understanding RowHammer and RowPress bitflips, and 2) identify key modeling and simulation parameters that significantly affect whether simulation results match real-chip characterization. We discuss implications for 1) rigorous, comprehensive, and efficient experimental characterization methodologies of DRAM read disturbance bitflips, and 2) the design of DRAM read disturbance mitigation techniques.
