arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2003.11018cs.AR
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一种用于可靠高性能众核3D- NoC系统的低开销软硬容错架构、设计和管理方案

A low-overhead soft-hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems

Khanh N Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah

摘要:

片上网络(NoC)范式已被提出作为一个有利的解决方案,以处理越来越多的核之间的严格的通信要求在一个单一的芯片上。然而,NoC系统暴露于晶体管的急剧缩小、低工作电压以及高集成度和功率密度,使得它们容易受到永久(硬)故障和瞬时(软)错误的影响。NoC中的硬故障可能导致外部阻塞,从而导致整个网络的拥塞。软错误更具挑战性,因为它的无声数据损坏,这会导致由于错误传播,数据包重传和死锁而导致大面积的错误数据。在本文中,我们提出了一个全面的软错误和硬容错的3D-NoC系统,命名为3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC(3D-FETO)的体系结构和设计。借助于有效的机制和算法,3D-FETO能够检测并从路由流水线级中发生的软错误中恢复,并利用可重新配置的组件来处理链路、输入缓冲区和交叉开关中的永久性故障。深入的评估结果表明,3D-FETO系统能够解决不同类型的硬故障和软错误,确保适度的性能下降,同时最大限度地减少额外的硬件复杂性并保持功率效率。

英文摘要:

The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution to handle the strict communication requirements between the increasingly large number of cores on a single chip. However, NoC systems are exposed to the aggressive scaling down of transistors, low operating voltages, and high integration and power densities, making them vulnerable to permanent (hard) faults and transient (soft) errors. A hard fault in a NoC can lead to external blocking, causing congestion across the whole network. A soft error is more challenging because of its silent data corruption, which leads to a large area of erroneous data due to error propagation, packet re-transmission, and deadlock. In this paper, we present the architecture and design of a comprehensive soft error and hard fault-tolerant 3D-NoC system, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid of efficient mechanisms and algorithms, 3D-FETO is capable of detecting and recovering from soft errors which occur in the routing pipeline stages and leverages reconfigurable components to handle permanent faults in links, input buffers, and crossbars. In-depth evaluation results show that the 3D-FETO system is able to work around different kinds of hard faults and soft errors, ensuring graceful performance degradation, while minimizing additional hardware complexity and remaining power efficient.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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