基于总线的二维多核系统和基于TSV的三维NOC众核系统的故障模型和容错方法综述
A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems
摘要：
可靠性在高性能计算处理器的开发中占据了中心地位。近年来，人们对建立故障和失效模型、理解失效机理和制定故障缓解策略以提高系统可靠性的兴趣激增。为了更好地理解辐射损伤、相关故障模型和故障影响，本文提出了一系列概念，并逐一加以说明。我们研究了基于数字CMOS设计和基于SRAM的FPGA的逻辑层最先进的故障缓解技术。CMOS SRAM结构对于数字CMOS和FPGA是相同的。了解基于FPGA的弹性SRAM对于开发弹性原型是必要的，它有助于更快地集成数字CMOS设计。在微体系结构和体系结构层，讨论了基于总线的多核系统的错误检测和恢复方法。基于硅通孔的3D片上网络是在单个芯片上集成多个内核的有前景的解决方案。一种适用于众核系统上千万亿次计算的互连方法。本文详细讨论了基于TSV的3D NOC众核系统的故障模型、故障机制、弹性3D路由器、容错方法等问题。研究了众核系统在硬件层次上的核冗余、自诊断和分布式诊断。本文介绍了多核和众核场景中从逻辑级到处理器核级的各种容错解决方案。
英文摘要：
Reliability has taken centre stage in the development of high-performance computing processors. A Surge of interest is noticeable in recent times in formulating fault and failure models, understanding failure mechanism and strategizing fault mitigation methods for improving the reliability of the system. The article presents a congregation of concepts illustrated one after the other for a better understanding of damages caused by radiation, relevant fault models, and effects of faults. We examine the state of art fault mitigation techniques at the logical layer for digital CMOS based design and SRAM based FPGA. CMOS SRAM structure is the same for both digital CMOS and FPGA. Understanding of resilient SRAM based FPGA is necessary for developing resilient prototypes and it facilitates a faster integration of digital CMOS designs. At the micro-architectural and architectural layer, error detection and recovery methods are discussed for bus-based multi-core systems. The Through silicon via based 3D Network on chip is the prospective solution for integrating many cores on single die. A suitable interconnection approach for petascale computing on many-core systems. The article presents an elaborate discussion on fault models, failure mechanisms, resilient 3D routers, defect tolerance methods for the TSV based 3D NOC many-core systems. Core redundancy, self-diagnosis and distributed diagnosis at the hardware level are examined for many-core systems. The article presents a gamut of fault tolerance solutions from logic level to processor core level in a multi-core and many-core scenario.
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