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arXiv 2609.01948cs.AR

一种基于新型非易失性存储器的片上训练架构:通过双极性权重分布缓解非理想效应

An Emerging NVM-Based On-Chip Training Architecture with Non-Ideality Mitigation Through Bipolar Weight Distributions

Peng Dang, Youna Huang, Yintao He, Huawei Li

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中文总结 AI 辅助

针对传统架构能效挑战及eNVM器件非理想性问题,提出NOVA架构与NAT算法,可显著提升片上训练精度与能效。

中文摘要 AI 辅助

深度学习的快速发展给传统冯·诺依曼架构带来了显著的能效挑战。基于新型非易失性存储器(eNVM)的存内计算(IMC)架构因高并行度和低功耗,被广泛视为加速神经网络训练的有前景方案。然而,eNVM器件的固有非理想性会导致电导更新偏离目标值,从而限制片上训练的性能。为应对这一挑战,本文提出一种用于片上训练的非理想性优化eNVM加速器(NOVA)架构。具体而言,我们首先制备了二维(2D)铁电场效应晶体管(FeFET),并开发了经实验数据校准的电导调制行为模型。基于该器件模型,我们首次提出了针对eNVM器件的非理想性规避训练(NAT)算法,该算法通过引导权重收敛至eNVM器件最稳定的电导区域,缓解精度下降。实验结果表明,即使在严重的器件不对称情况下,NAT在多个基准任务上的精度较基线方法平均提升15.1%;同时,NOVA的平均能效较图形处理单元(GPUs)的峰值能效提升约33.58倍。

英文摘要

The rapid advancement of deep learning has presented significant energy efficiency challenges to the conventional von Neumann architecture. In-memory computing (IMC) architectures based on emerging non-volatile memory (eNVM) are widely regarded as a promising solution for accelerating neural network training due to their high parallelism and low power consumption. However, the intrinsic non-idealities of eNVM devices can cause conductance updates to deviate from target values, thereby limiting the performance of on-chip training. To address this challenge, this paper presents a Non-ideality Optimized eNVM Accelerator (NOVA) architecture for on-chip training. Specifically, we first fabricate a two-dimensional (2D) ferroelectric field-effect transistor (FeFET) and develop a conductance modulation behavioral model calibrated with experimental data. Building upon this device model, we propose, for the first time, a Non-ideality Avoidance Training (NAT) algorithm tailored for eNVM devices, which mitigates accuracy degradation by guiding weight convergence toward the most stable conductance regions of eNVM devices. Experimental results demonstrate that, even under severe device asymmetry, NAT improves the accuracy by an average of 15.1\% over the baseline methods across multiple benchmark tasks. Meanwhile, the NOVA achieves an average energy efficiency gain of approximately 33.58$\times$ compared with the peak energy efficiency of graphics processing units (GPUs).

发表机构

  • State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences(中国科学院计算技术研究所处理器重点实验室)
  • University of Chinese Academy of Sciences(中国科学院大学)
  • Southern University of Science and Technology(南方科技大学)
  • Pengcheng Laboratory(鹏城实验室)

机构由 AI 辅助整理,请以论文原文为准。

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