Gate-Based High Fidelity Spin Read-out in a CMOS Device
Matias Urdampilleta, David J. Niegemann, Emmanuel Chanrion, Baptiste Jadot, Cameron Spence, Pierre-André Mortemousque, 1 Christopher Bäuerle, Louis Hutin, Benoi… 展开作者
Matias Urdampilleta, David J. Niegemann, Emmanuel Chanrion, Baptiste Jadot, Cameron Spence, Pierre-André Mortemousque, 1 Christopher Bäuerle, Louis Hutin, Benoit Bertrand, Sylvain Barraud, Romain Maurand, Marc Sanquer, Xavier Jehl, Silvano De Franceschi, Maud Vinet, Tristan Meunier
The engineering of electron spin qubits in a compact unit cell embedding all quantum functionalities is mandatory for large scale integration. In particular, the development of a high-fidelity and scalable spin readout method remains an open challenge. Here we demonstrate high-fidelity and robust spin readout based on gate reflectometry in a CMOS device comprising one qubit dot and one ancillary dot coupled to an electron reservoir to perform readout. This scalable method allows us to read out a spin with a fidelity above 99% for 1 ms integration time. To achieve such fidelity, we exploit a latched spin blockade mechanism that requires electron exchange between the ancillary dot and the reservoir. We show that the demonstrated high read-out fidelity is fully preserved up to 0.5 K. This results holds particular relevance for the future co-integration of spin qubits and classical control electronics.
We report the first quantum bit device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself.
The advanced nanoscale integration available in silicon complementary metal-oxide-semiconductor (CMOS) technology provides a key motivation for its use in spin-based quantum computing applications. Initial demonstrations of quantum dot formation and spin blockade in CMOS foundry-compatible devices are encouraging, but results are yet to match the control of individual electrons demonstrated in university-fabricated multi-gate designs. We show here that the charge state of quantum dots formed in a CMOS nanowire device can be sensed by using floating gates to electrostatically couple it to a rem…
In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design…
We report on DC and microwave electrical transport measurements in silicon-on-insulator CMOS nano-transistors at low and room temperature. At low source-drain voltage, the DC current and RF response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature is accurately fitted by a thermionic model. From the fits…
In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying…
We report fast charge state readout of a double quantum dot in a CMOS split-gate silicon nanowire transistor via the large dispersive interaction with microwave photons in a lumped-element resonator formed by hybrid integration with a superconducting inductor. We achieve a coupling rate $g_0/(2π) = 204 \pm 2$ MHz by exploiting the large interdot gate lever arm of an asymmetric split-gate device, $α=0.72$, and by inductively coupling to the resonator to increase its impedance, $Z_\text{r}=560~Ω$. In the dispersive regime, the large coupling strength at the double quantum dot hybridisation point…
Quantum computing technology is maturing at a relentless pace, yet individual quantum bits are wired one by one. As quantum processors become more complex, they require efficient interfaces to deliver signals for control and readout while keeping the number of inputs manageable. Digital electronics offers solutions to the scaling challenge by leveraging established industrial infrastructure and applying it to integrate silicon-based quantum devices with conventional CMOS circuits. Here, we combine both technologies at milikelvin temperatures and demonstrate the building blocks of a dynamic ran…
Quantum computers require interfaces with classical electronics for efficient qubit control, measurement and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offer potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-transistor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large scale circui…
Silicon spin qubits are promising candidates for realising large scale quantum processors, benefitting from a magnetically quiet host material and the prospects of leveraging the mature silicon device fabrication industry. We report the measurement of an electron spin in a singly-occupied gate-defined quantum dot, fabricated using CMOS compatible processes at the 300 mm wafer scale. For readout, we employ spin-dependent tunneling combined with a low-footprint single-lead quantum dot charge sensor, measured using radiofrequency gate reflectometry. We demonstrate spin readout in two devices usin…
We present electrical data of silicon single electron devices fabricated with CMOS techniques and protocols. The easily tuned devices show clean Coulomb diamonds at T = 30 mK and charge offset drift of 0.01 e over eight days. In addition, the devices exhibit robust transistor characteristics including uniformity within about 0.5 V in the threshold voltage, gate resistances greater than 10 GΩ, and immunity to dielectric breakdown in electric fields as high as 4 MV/cm. These results highlight the benefits in device performance of a fully CMOS process for single electron device fabrication.
In the strive for scalable quantum processors, significant effort is being devoted to the development of cryogenic classical hardware for the control and readout of a growing number of qubits. Here we report on a cryogenic circuit incorporating a CMOS-based active inductor enabling fast impedance measurements with a sensitivity of 10 aF and an input-referred noise of 3.7 aF/sqrt(Hz). This type of circuit is especially conceived for the readout of semiconductor spin qubits. As opposed to commonly used schemes based on dispersive rf reflectometry, which require mm-scale passive inductors, it all…
Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defin…
We report CMOS-compatible quantized current sources (electron pumps) fabricated with nanowires (NWs) on 300 mm SOI wafers. Unlike other Al, GaAs or Si based metallic or semiconductor pumps, the fabrication does not rely on electron-beam lithography. The structure consists of two gates in series on the nanowire and the only difference with the SOI nanowire process lies in long (40 nm) nitride spacers. As a result a single, silicided island gets isolated between the gates and transport is dominated by Coulomb blockade at cryogenic temperatures thanks to the small size and therefore capacitance o…
We successfully demonstrated experimentally the electrical-field-mediated control of the spin of electrons confined in an SOI Quantum Dot (QD) device fabricated with a standard CMOS process flow. Furthermore, we show that the Back-Gate control in SOI devices enables switching a quantum bit (qubit) between an electrically-addressable, yet charge noise-sensitive configuration, and a protected configuration.
Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of good electrostatic control together with a high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10 nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge or III-V and dimensional scaling is expected to end around 12 nm gate-length. We demonstrate that u…
Solid-state quantum computers require classical electronics to control and readout individual qubits and to enable fast classical data processing [1-3]. Integrating both subsystems at deep cryogenic temperatures [4], where solid-state quantum processors operate best, may solve some major scaling challenges, such as system size and input/output (I/O) data management [5]. Spin qubits in silicon quantum dots (QDs) could be monolithically integrated with complementary metal-oxide-semiconductor (CMOS) electronics using very-large-scale integration (VLSI) and thus leveraging over wide manufacturing …
We show how to measure and manipulate a single spin in a CMOS device fabricated in a pre-industrial 300 mm CMOS foundry. The device can be used as a spin quantum bit working at very low temperature. The spin manipulation is done by a microwave electric field applied directly on a gate. The presented results are a proof-of-principle demonstration of the possibility to define qubits by means of conventional industrial fabrication processes.
One of the main advantages of silicon spin qubits over other solid-state qubits is their inherent scalability and compatibility with the 300 mm CMOS fabrication technology that is already widely used in the semiconductor industry, whilst maintaining high readout and gate fidelities. We demonstrate detection of a single electron spin using energy-selective readout in a CMOS-fabricated nanowire device with an integrated charge detector. We measure a valley splitting of 0.3 meV and 0.16 meV in two similar devices. The anisotropy of the spin-valley mixing is measured and shown to follow the depend…
Low temperature electron transport measurements of single electron transistors fabricated in advanced CMOS technology with polysilicon gates not only exhibit clear Coulomb blockade behavior but also show a large number of additional conductance fluctuations in the nonlinear regime. By comparison with simulations these features are quantitatively attributed to the effects of discretely charged islands in the polysilicon gates.
Complementary metal oxide semiconductor (CMOS) logic circuits at the ultimate scaling limit place the utmost demands on the properties of all materials involved. The requirements for semiconductors are well explored and could possibly be satisfied by a number of layered two-dimensional (2D) materials, like for example transition-metal dichalcogenides or black phosphorus. The requirements for the gate insulator are arguably even more challenging and difficult to meet. In particular the combination of insulator to semiconductor which forms the central element of the metal oxide semiconductor fie…
Silicon quantum dots are attractive candidates for the development of scalable, spin-based qubits. Pauli spin blockade in double quantum dots provides an efficient, temperature independent mechanism for qubit readout. Here we report on transport experiments in double gate nanowire transistors issued from a CMOS process on 300 mm silicon-on-insulator wafers. At low temperature the devices behave as two few-electron quantum dots in series. We observe signatures of Pauli spin blockade with a singlet-triplet splitting ranging from 0.3 to 1.3 meV. Magneto-transport measurements show that transition…
Spin torque majority gates are modeled and several regimes of magnetization switching (some leading to failure) are discovered. The switching speed and noise margins are determined for STMGs and an adder based on it. With switching time of 3ns at current of 80uA, the adder computational throughput is comparable to that of a CMOS adder.
Compact modeling of inter-device radiation-induced leakage underneath the gateless thick STI oxide is presented and validated taking into account CMOS technology and hardness parameters, dose-rate and annealing effects, and dependence on electric modes under irradiation. It was shown that proposed approach can be applied for description of dose dependent static leakage currents in complex FPGA circuits.
We present a novel hybrid CMOS-MQCA architecture using multi-layer Spintronic devices as computing elements. A feasibility study is presented with 22nm CMOS where new approaches for spin transfer torque induced clocking and read-out scheme for variability-tolerance are introduced. A first-of-its-kind Spintronic device model enables circuit simulation using existing CAD infrastructure. Approximately 70% reduction in energy consumption is observed when compared against conventional field-induced clocking scheme.
A new spin based logic device is proposed. It is comprised of a common free ferromagnetic layer separated by a tunnel junction from three inputs and one output with separate fixed layers. It has the functionality of a majority gate and is switched by spin transfer torque. Validity of its logic operation is demonstrated by micromagnetic simulation. A version of such devices with perpendicular magnetization is examined. Switching encompasses moving domain walls. The device reuses most of the materials and structures from spin torque RAM, and is entirely compatible with CMOS technology.
Having multi-output logic gates saves much energy because the same structure can be used to feed multiple inputs of next stage gates simultaneously. This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection. The proposed logic gates are validated by means of micromagnetic simulations. Furthermore, the energy and delay are estimated for the proposed structures and compared with the state-of-the-art spin wave logic gates, and 16nm and 7nm CMOS. The results demons…
Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as tunnelling and coherence, can be harnessed to use existing CMOS technology for quantum information processing. Here, we report the observation of coherent charge oscillations in a double quantum dot formed in a silicon nanowire transistor detected via its dispersive interaction with a radio-frequency resonant circuit coupled via the gate. Differential capacitan…
The end of Moore's law for CMOS technology has prompted the search for low-power computing alternatives, resulting in several promising proposals based on magnetic logic[1-8]. One approach aims at tailoring arrays of nanomagnetic islands in which the magnetostatic interactions constrain the equilibrium orientation of the magnetization to embed logical functionalities[9-12]. Despite the realization of several proofs of concepts of such nanomagnetic logic[13-15], it is still unclear what the advantages are compared to the widespread CMOS designs, due to their need for clocking[16, 17] and/or the…
By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the $3$-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionali…
The quality of the semiconductor-barrier interface plays a pivotal role in the demonstration of high quality reproducible quantum dots for quantum information processing. In this work, we have measured SiMOSFET Hall bars on undoped Si substrates in order to investigate the quality of the devices fabricated in a full CMOS process. We report a record mobility of 17'500 cm2/Vs with a sub-10 nm oxide thickness indicating a high quality interface, suitable for future qubit applications. We also study the influence of gate materials on the mobilities and discuss the underlying mechanisms, giving ins…
The construction of quantum computer simulators requires advanced software which can capture the most significant characteristics of the quantum behavior and quantum states of qubits in such systems. Additionally, one needs to provide valid models for the description of the interface between classical circuitry and quantum core hardware. In this study, we model electron transport in semiconductor qubits based on an advanced CMOS technology. Starting from 3D simulations, we demonstrate an order reduction and the steps necessary to obtain ordinary differential equations on probability amplitudes…
By their very nature, Spin Waves (SWs) consume ultra-low amounts of energy, which makes them suitable for ultra-low energy consumption applications. In addition, a compressor can be utilized to further reduce the energy consumption and enhance the speed of a multiplier. Therefore, we propose a novel energy efficient SW based 4-2 compressor consisting of 4 XOR gates and 2 Majority gates. The proposed compressor is validated by means of micromagnetic simulations and compared with the state-of-the-art SW, 22nm CMOS, Magnetic Tunnel Junction (MTJ), Domain Wall Motion (DWM), and Spin-CMOS technolog…
In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry…
Spin Waves (SWs) propagate through magnetic waveguides and interfere with each other without consuming noticeable energy, which opens the road to new ultra-low energy circuit designs. In this paper we build upon SW features and propose a novel energy efficient Full Adder (FA) design consisting of The FA 1 Majority and 2 XOR gates, which outputs Sum and Carry-out are generated by means of threshold and phase detection, respectively. We validate our proposal by means of MuMax3 micromagnetic simulations and we evaluate and compare its performance with state-of-the-art SW, 22nm CMOS, Magnetic Tunn…
Scalability from single qubit operations to multi-qubit circuits for quantum information processing requires architecture-specific implementations. Semiconductor hybrid qubit architecture is a suitable candidate to realize large scale quantum information processing, as it combines a universal set of logic gates with fast and all-electrical manipulation of qubits. We propose an implementation of hybrid qubits, based on Si Metal-Oxide-Semiconductor (MOS) quantum dots, compatible with the CMOS industrial technologic standards. We discuss the realization of multi-qubit circuits capable of fault-to…
This paper provides a tutorial overview over recent vigorous efforts to develop computing systems based on spin waves instead of charges and voltages. Spin-wave computing can be considered as a subfield of spintronics, which uses magnetic excitations for computation and memory applications. The tutorial combines backgrounds in spin-wave and device physics as well as circuit engineering to create synergies between the physics and electrical engineering communities to advance the field towards practical spin-wave circuits. After an introduction to magnetic interactions and spin-wave physics, all…
Analytical solutions describing quantum swap and Hadamard gate are given with the use of tight-binding approximation. Decoherence effects are described analytically for two interacting electrons confined by local potentials with use of tight-binding simplistic model and in Schroedinger formalism with omission of spin degree of freedom. The obtained results can be generalized for the case of N electrostatically interacting quantum bodies confined by local potentials (N-qubit) system representing any electrostatic quantum gate with N1/N-N1 inputs/outputs. The mathematical structure of system evo…
Graphene holds a great promise for a number of diverse future applications, in particular related to its easily tunable doping and Fermi level by electrostatic gating. However, as of today, most implementations rely on electrical doping via the application of continuous large voltages to maintain the desired doping. We show here how graphene can be implemented with conventional semiconductor flash memory technology in order to make programmable doping possible, simply by the application of short gate pulses. We also demonstrate how this approach can be used for a memory device, and also show p…
