By means of catalytic chemical vapor deposition (CCVD) in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate without the need to transfer graphene layers. In-situ grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios. In contrast, BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1E7. The complete fabrication process is silicon CMOS compatible. This will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.
We invented a novel method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. By means of catalytic chemical vapor deposition (CCVD) the in-situ grown bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g. temperature and gas mixture. BiLGFETs exhibit ultra-high on/off-current ratios of 107 at room temperature, exceeding previously reported values by several orders of magnitude. This will allow a …
We invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane based growth process monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby t…
We explore phonon-mediated quantum transport through electronic noise characterization of a commercial CMOS transistor. The device behaves as a single electron transistor thanks to a single impurity atom in the channel. A low noise cryogenic CMOS transimpedance amplifier is exploited to perform low-frequency noise characterization down to the single electron, single donor and single phonon regime simultaneously, not otherwise visible through standard stability diagrams. Single electron tunneling as well as phonon-mediated features emerges in rms-noise measurements. Phonons are emitted at high …
We report on DC and microwave electrical transport measurements in silicon-on-insulator CMOS nano-transistors at low and room temperature. At low source-drain voltage, the DC current and RF response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature is accurately fitted by a thermionic model. From the fits…
Process-related and stress-induced changes in threshold voltage are major variability concerns in ultra-scaled CMOS transistors. The device designers consider this variability as an irreducible part of the design problem and use different circuit level optimization schemes to handle these variations. In this paper, we demonstrate how an increase in the negative steepness of the universal mobility relationship improves both the process-related (e.g., oxide thickness fluctuation, gate work-function fluctuation), as well as stress-induced or reliability-related (e.g., Bias Temperature Instability…
Single-electron transistors (SETs) have been extensively used as charge sensors in many areas such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal-oxide semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge these signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated C…
We report strategies of achieving both high assembly yield of carbon nanotubes at selected position of the circuit via dielectrophoresis (DEP) and field effect transistor (FET) yield using semiconducting enriched single walled carbon nanotube (s-SWNT) aqueous solution. When the DEP parameters were optimized for the assembly of individual s-SWNT, 97% of the devices show FET behavior with a maximum mobility of 210 cm2/Vs, on-off current ratio ~ 106 and on conductance up to 3 μS, however with an assembly yield of only 33%. As the DEP parameters were optimized so that 1-5 s-SWNTs are connected per…
Temperature is a fundamental parameter in the study of physical phenomena. At the nanoscale, local temperature differences can be harnessed to design novel thermal nanoelectronic devices or test quantum thermodynamical concepts. Determining temperature locally is hence of particular relevance. Here, we present a primary electron thermometer that allows probing the local temperature of a single electron reservoir in single-electron devices. The thermometer is based on cyclic electron tunneling between a system with discrete energy levels and a single electron reservoir. When driven at a finite …
In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design…
Silicon-On-Insulator nanowire transistors of very small dimensions exhibit quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for larger dimensions, allowing to design integrated circuits. Using the same process, we have co-integrated a FET-based ring oscillator circuit operating at cryogenic temperature which generates a radio-frequency (RF) signal on the gate of a nanoscale device showing Coulomb oscillations. We observe rectification of the RF signal, in good agreement with modeling.
In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying…
Quantum computers require interfaces with classical electronics for efficient qubit control, measurement and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offer potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-transistor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large scale circui…
Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of good electrostatic control together with a high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10 nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge or III-V and dimensional scaling is expected to end around 12 nm gate-length. We demonstrate that u…
One consequence of the continued downwards scaling of transistors is the reliance on only a few discrete atoms to dope the channel, and random fluctuations of the number of these dopants is already a major issue in the microelectonics industry. While single-dopant signatures have been observed at low temperature, studying the impact of only one dopant up to room temperature requires extremely small lengths. Here, we show that a single arsenic dopant dramatically affects the off-state behavior of an advanced microelectronics field effect transistor (FET) at room temperature. Furthermore, the io…
A fresh look on carbon-based transistor channel materials like single-walled carbon nanotubes (CNT) and graphene nanoribbons (GNR) in future electronic applications is given. Although theoretical predictions initially promised that GNR (which do have a bandgap) would perform equally well as transistors based on CNTs, experimental evidence for the well-behaved transistor action is missing up to now. Possible reasons for the shortcomings as well as possible solutions to overcome the performance gap will be addressed. In contrast to GNR, short channel CNT field effect transistors (FET) demonstrat…
Low temperature electron transport measurements of single electron transistors fabricated in advanced CMOS technology with polysilicon gates not only exhibit clear Coulomb blockade behavior but also show a large number of additional conductance fluctuations in the nonlinear regime. By comparison with simulations these features are quantitatively attributed to the effects of discretely charged islands in the polysilicon gates.
We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 $\times$ 20 nm$^{2}$ is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement…
We present electrical data of silicon single electron devices fabricated with CMOS techniques and protocols. The easily tuned devices show clean Coulomb diamonds at T = 30 mK and charge offset drift of 0.01 e over eight days. In addition, the devices exhibit robust transistor characteristics including uniformity within about 0.5 V in the threshold voltage, gate resistances greater than 10 GΩ, and immunity to dielectric breakdown in electric fields as high as 4 MV/cm. These results highlight the benefits in device performance of a fully CMOS process for single electron device fabrication.
This paper reports on the improvement of the differential current gain in the spin-torque transistor based on two independent innovations, viz.the use of magnetic insulators and the spin Hall effect. Since, except for a few examples, spin transistors lack the current gain that is essential for many applications, spintronics and magnetic information technology lack an essential functionality compared to CMOS devices. Here, we show that negative differential resistance and large differential gain is possible in a large region of parameter space of the spin torque transistor. We also demonstrate …
This paper reviews the current status of graphene transistors as potential supplement to silicon CMOS technology. A short overview of graphene manufacturing and metrology methods is followed by an introduction of macroscopic graphene field effect transistors (FETs). The absence of an energy band gap is shown to result in severe shortcomings for logic applications. Possibilities to engineer a band gap in graphene FETs including quantum confinement in graphene Nanoribbons (GNRs) and electrically or substrate induced asymmetry in double and multi layer graphene are discussed. Graphene FETs are sh…
Recent experiments shown that graphene epitaxially grown on Silicon Carbide (SiC) can exhibit a energy gap of 0.26 eV, making it a promising material for electronics. With an accurate model, we explore the design parameter space for a fully ballistic graphene-on-SiC Tunnel Field-Effect Transistors (TFETs), and assess the DC and high frequency figures of merit. The steep subthreshold behavior can enable I_{ON}/I_{OFF} ratios exceeding 10^4 even with a low supply voltage of 0.15 V, for devices with gatelength down to 30 nm. Intrinsic transistor delays smaller than 1 ps are obtained. These factor…
Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as tunnelling and coherence, can be harnessed to use existing CMOS technology for quantum information processing. Here, we report the observation of coherent charge oscillations in a double quantum dot formed in a silicon nanowire transistor detected via its dispersive interaction with a radio-frequency resonant circuit coupled via the gate. Differential capacitan…
In 1963, Moll and Tarui suggested that the field-effect conductance of a semiconductor could be controlled by the remanent polarization of a ferroelectric (FE) material to create a ferroelectric field-effect transistor (FE-FET). However, subsequent efforts to produce a practical, compact FE-FET have been plagued by low retention and incompatibility with Complementary Metal Oxide Semiconductor (CMOS) process integration. These difficulties led to the development of trapped-charge based memory devices (also called floating gate or flash memory), and these are now the mainstream non-volatile memo…
In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establ…
Silicon quantum dots are attractive candidates for the development of scalable, spin-based qubits. Pauli spin blockade in double quantum dots provides an efficient, temperature independent mechanism for qubit readout. Here we report on transport experiments in double gate nanowire transistors issued from a CMOS process on 300 mm silicon-on-insulator wafers. At low temperature the devices behave as two few-electron quantum dots in series. We observe signatures of Pauli spin blockade with a singlet-triplet splitting ranging from 0.3 to 1.3 meV. Magneto-transport measurements show that transition…
In this paper we propose two transistor concepts based on lateral heterostructures of monolayer MoS$_2$, composed of adjacent regions of 1T (metallic) and 2H (semiconducting) phases, inspired by recent research showing the possibility to obtain such heterostructures by electron beam irradiation. The first concept, the lateral heterostructure field-effect transistor, exhibits potential of better performance with respect to the foreseen evolution of CMOS technology, both for high performance and low power applications. Performance potential has been evaluated by means of detailed multi-scale mat…
Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at temperatures ranging from 300K down to 4.2K. We extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. In addition to their I-V characteristics, threshold voltage(Vth) values, on/off current ratio, transconductance of the MOS transistors, and resistors on chips are measured at temperatures from 300K down to …
We report on the fabrication and electrical characterization at millikelvin temperatures of a novel silicon single-electron transistor (Si-SET). The island and source-drain leads of the Si-SET are formed by the implantation of phosphorus ions to a density above the metal-insulator-transition, with the tunnel junctions created by undoped regions. Surface gates above each of the tunnel junctions independently control the tunnel coupling between the Si-SET island and leads. The device shows periodic Coulomb blockade with a charging energy e$^2$/2C$_Σ$ $\sim$ 250 $μ$eV, and demonstrates a reproduc…
We numerically investigate the possibility of using Tunnel field-effect transistor (TFET) in a 32 kHz crystal oscillator circuit to reduce power consumption. A simulation using SPICE (Simulation Program with Integrated Circuit Emphasis) is carried out based on a conventional CMOS transistor model. It is shown that the power consumption of TFET is one-tenth that of conventional low-power CMOS.
CMOS + stochastic nanomagnets: heterogeneous computers for probabilistic inference and learning
University of California Santa Barbara（加州大学圣巴巴拉分校）；Tohoku University（东北大学）；Research Institute of Electrical Communication, Tohoku University（东北大学电气通信研究所）；Graduate School of Engineering, Tohoku University（东北大学工学研究科）
The advanced nanoscale integration available in silicon complementary metal-oxide-semiconductor (CMOS) technology provides a key motivation for its use in spin-based quantum computing applications. Initial demonstrations of quantum dot formation and spin blockade in CMOS foundry-compatible devices are encouraging, but results are yet to match the control of individual electrons demonstrated in university-fabricated multi-gate designs. We show here that the charge state of quantum dots formed in a CMOS nanowire device can be sensed by using floating gates to electrostatically couple it to a rem…
In this work, double-gated field effect transistors manufactured from monolayer graphene are investigated. Conventional top-down CMOS-compatible processes are applied except for graphene deposition by manual exfoliation. Carrier mobilities in single- and double gated graphene field effect transistors are compared. Even in double-gated graphene FETs, the carrier mobility exceeds the universal mobility of silicon over nearly the entire measured range. At comparable dimensions, reported mobilities for ultra thin body silicon-on-insulator MOSFETs can not compete with graphene FET values.
3D NAND enables continuous NAND density and cost scaling beyond conventional 2D NAND. However, its poly-Si channel suffers from low mobility, large device variations, and instability caused by grain boundaries. Here, we overcome these drawbacks by introducing an amorphous indium-gallium-zinc-oxide (a-IGZO) channel, which has the advantages of ultra-low OFF current, back-end-of-line compatibility, higher mobility and better uniformity than poly-Si, and free of grain boundaries due to the amorphous nature. Ultra-scaled floating-gate (FG) transistors with a channel length of 60 nm are reported, a…
The recent development of arrays of quantum dots in semiconductor nanostructures highlights the progress of quantum devices toward large scale. However, how to realize such arrays on a scalable platform such as silicon is still an open question. One of the main challenge resides in the detection of charges within the array. It is a prerequisite functionality to initialize a desired charge state and readout spins through spin-to-charge conversion mechanisms. In this paper, we use two methods based on either a single-lead charge detector, or a reprogrammable single electron transistor. Thanks to…
Intimate integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrently with enhanced energy efficiency in big-data applications such as artificial intelligence. Despite decades of efforts, reliable, compact, energy efficient and scalable memory devices are elusive. Ferroelectric Field Effect Transistors (FE-FETs) are a promising candidate but their scalability and performance in a back-end-of-line (BEOL) process remain unattained. Here, we present scalable BEOL compatible FE-FETs …
Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defin…
All Spin Logic gates employ multiple nano-magnets interacting through spin-torque using non-magnetic channels. Compactness, non-volatility and ultra-low voltage operation are some of the attractive features of ASL, while, low switching-speed (of nano-magnets as compared to CMOS gates) and static-power dissipation can be identified as the major bottlenecks. In this work we explore design techniques that leverage the specific device characteristics of ASL to overcome the inefficiencies and to enhance the merits of this technology, for a given set of device parameters. We exploit the non-volatili…
Scalability in the fabrication and operation of quantum computers is key to move beyond the NISQ era. So far, superconducting transmon qubits based on aluminum Josephson tunnel junctions have demonstrated the most advanced results, though this technology is difficult to implement with large-scale facilities. An alternative "gatemon" qubit has recently appeared, which uses hybrid superconducting/semiconducting (S/Sm) devices as gate-tuned Josephson junctions. Current implementations of these use nanowires however, of which the large-scale fabrication has not yet matured either. A scalable gatem…
Recent advances in quantum error correction (QEC) codes for fault-tolerant quantum computing \cite{Terhal2015} and physical realizations of high-fidelity qubits in a broad range of platforms \cite{Kok2007, Brown2011, Barends2014, Waldherr2014, Dolde2014, Muhonen2014, Veldhorst2014} give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based entirely on complementary metal-oxide-semiconductor (…
The past decade has seen rapid growth in the research area of graphene and its application to novel electronics. With Moore's law beginning to plateau, the need for post-silicon technology in industry is becoming more apparent. Moreover, existing technology is insufficient for implementing terahertz detectors and receivers, which are required for a number of applications including medical imaging and security scanning. Graphene is considered to be a key potential candidate for replacing silicon in existing CMOS technology as well as realizing field effect transistors for terahertz detection, d…
In this work, we demonstrate high performance indium-tin-oxide (ITO) transistors with the channel thickness down to 1 nm and ferroelectric Hf0.5Zr0.5O2 as gate dielectric. On-current of 0.243 A/mm is achieved on sub-micron gate-length ITO transistors with a channel thickness of 1 nm, while it increases to as high as 1.06 A/mm when the channel thickness increases to 2 nm. A raised source/drain structure with a thickness of 10 nm is employed, contributing to a low contact resistance of 0.15 Ωmm and a low contact resistivity of 1.1{\times}10-7 Ωcm2. The ITO transistor with a recessed channel and …
The celebrated electronic properties of graphene have opened way for materials just one-atom-thick to be used in the post-silicon electronic era. An important milestone was the creation of heterostructures based on graphene and other two-dimensional (2D) crystals, which can be assembled in 3D stacks with atomic layer precision. These layered structures have already led to a range of fascinating physical phenomena, and also have been used in demonstrating a prototype field effect tunnelling transistor - a candidate for post-CMOS technology. The range of possible materials which could be incorpo…
