Silicon-On-Insulator nanowire transistors of very small dimensions exhibit quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for larger dimensions, allowing to design integrated circuits. Using the same process, we have co-integrated a FET-based ring oscillator circuit operating at cryogenic temperature which generates a radio-frequency (RF) signal on the gate of a nanoscale device showing Coulomb oscillations. We observe rectification of the RF signal, in good agreement with modeling.
This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300, 77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced b…
This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2\,K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4\,K and 4.2\,K respectively, using a recently…
Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at temperatures ranging from 300K down to 4.2K. We extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. In addition to their I-V characteristics, threshold voltage(Vth) values, on/off current ratio, transconductance of the MOS transistors, and resistors on chips are measured at temperatures from 300K down to …
In the strive for scalable quantum processors, significant effort is being devoted to the development of cryogenic classical hardware for the control and readout of a growing number of qubits. Here we report on a cryogenic circuit incorporating a CMOS-based active inductor enabling fast impedance measurements with a sensitivity of 10 aF and an input-referred noise of 3.7 aF/sqrt(Hz). This type of circuit is especially conceived for the readout of semiconductor spin qubits. As opposed to commonly used schemes based on dispersive rf reflectometry, which require mm-scale passive inductors, it all…
Solid-state quantum computers require classical electronics to control and readout individual qubits and to enable fast classical data processing [1-3]. Integrating both subsystems at deep cryogenic temperatures [4], where solid-state quantum processors operate best, may solve some major scaling challenges, such as system size and input/output (I/O) data management [5]. Spin qubits in silicon quantum dots (QDs) could be monolithically integrated with complementary metal-oxide-semiconductor (CMOS) electronics using very-large-scale integration (VLSI) and thus leveraging over wide manufacturing …
This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell-Boltzmann approximation is demonstrated in the limit to zero Kelvin as a result of dopant freeze-out in cryogenic equilibrium. Explicit MOS transistor expressions are then derived including incomplete dopant-ionization, bandgap w…
The most promising quantum algorithms require quantum processors hosting millions of quantum bits when targeting practical applications. A major challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, a major bottleneck appears between the quantum chip in a dilution refrigerator and the room temperature electronics. Advanced lithography supports the fabrication of both CMOS control electronics and qubits in silicon. When the electronics are designed to operate at cryogenic temperatures, it can ultimately be integrated with…
We report CMOS-compatible quantized current sources (electron pumps) fabricated with nanowires (NWs) on 300 mm SOI wafers. Unlike other Al, GaAs or Si based metallic or semiconductor pumps, the fabrication does not rely on electron-beam lithography. The structure consists of two gates in series on the nanowire and the only difference with the SOI nanowire process lies in long (40 nm) nitride spacers. As a result a single, silicided island gets isolated between the gates and transport is dominated by Coulomb blockade at cryogenic temperatures thanks to the small size and therefore capacitance o…
Process-related and stress-induced changes in threshold voltage are major variability concerns in ultra-scaled CMOS transistors. The device designers consider this variability as an irreducible part of the design problem and use different circuit level optimization schemes to handle these variations. In this paper, we demonstrate how an increase in the negative steepness of the universal mobility relationship improves both the process-related (e.g., oxide thickness fluctuation, gate work-function fluctuation), as well as stress-induced or reliability-related (e.g., Bias Temperature Instability…
This paper presents a physics-based model for the threshold voltage in bulk MOSFETs valid from room down to cryogenic temperature (4.2 K). The proposed model is derived from Poisson's equation including bandgap widening, intrinsic carrier-density scaling, and incomplete ionization. We demonstrate that accounting for incomplete ionization in the expression of the threshold voltage is critical for an accurate estimation of the current. The model is validated with our experimental results from nMOSFETs of a 28-nm CMOS process. The developed model is a key element for a cryo-CMOS compact model and…
Previous cryogenic electronics studies are most above 4.2K. In this paper we present the cryogenic characterization of a 0.18μm standard bulk CMOS technology(1.8V and 5V) at sub-kelvin temperature around 270mK. PMOS and NMOS devices with different width to length ratios(W/L) are tested and characterized under various bias conditions at temperatures from 300K to 270mK. It is shown that the 0.18μm standard bulk CMOS technology is still working at sub-kelvin temperature. The kink effect and current overshoot phenomenon are observed at sub-kelvin temperature. Especially, current overshoot phenomen…
Single-electron transistors (SETs) have been extensively used as charge sensors in many areas such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal-oxide semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge these signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated C…
The control interface of a large-scale quantum computer will likely require electronic sub-systems that operate in close proximity to the qubits, at deep cryogenic temperatures. Here, we report the low-temperature performance of custom cryo-CMOS band-gap reference circuits designed to provide stable voltages and currents on-chip, independent of local temperature fluctuations. Our circuits are fabricated in 0.35 um silicon Germanium (SiGe) BiCMOS and 28 nm Fully Depleted Silicon On Insulator (FDSOI) CMOS processes, and we compare the performance of each. Beyond their specific application as low…
Integrated circuits based on CMOS (complementary metal-oxide semiconductors) are at the heart of the technological revolution of the past 40 years, as these have enabled compact and low cost micro-electronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible light cameras has been impeded by the difficulty to combine other semiconductors than silicon with CMOS. Here, we show for the first time the monolithic integration of a CMOS integrated circuit with graphene, operating as a high mobility phototransistor. We dem…
We explore phonon-mediated quantum transport through electronic noise characterization of a commercial CMOS transistor. The device behaves as a single electron transistor thanks to a single impurity atom in the channel. A low noise cryogenic CMOS transimpedance amplifier is exploited to perform low-frequency noise characterization down to the single electron, single donor and single phonon regime simultaneously, not otherwise visible through standard stability diagrams. Single electron tunneling as well as phonon-mediated features emerges in rms-noise measurements. Phonons are emitted at high …
Compact modeling of inter-device radiation-induced leakage underneath the gateless thick STI oxide is presented and validated taking into account CMOS technology and hardness parameters, dose-rate and annealing effects, and dependence on electric modes under irradiation. It was shown that proposed approach can be applied for description of dose dependent static leakage currents in complex FPGA circuits.
In the early stages of a novel technology development, it is difficult to provide a comprehensive assessment of its potential capabilities and impact. Nevertheless, some preliminary estimates can be drawn and are certainly of great interest and in this paper we follow this line of reasoning within the framework of the Spin Wave (SW) computing paradigm. In particular, we are interested in assessing the technological development horizon that needs to be reached in order to unleash the full SW paradigm potential such that SW circuits can outperform CMOS counterparts in terms of energy consumption…
The inter-device mismatch and intra-device temporal instability in the nanoscale CMOS circuits is examined from a unified point of view as a static and dynamic parts of the variability con-cerned with stochastic oxide charge trapping and de-trapping. This approach has been benchmarked on the recent evidence of the radiation-induced increase of inter-transistor mismatch in 60 nm ICs. A possible reliability limitation in ultrascale circuits concerned with the single or a few charged defect instability is pointed out and estimated.
Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the CMOS roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.
A robust cryogenic infrastructure in form of a wired, thermally optimized dilution refrigerator is essential for present and future solid-state based quantum processors. Here, we engineer an extensible cryogenic setup, which minimizes passive and active heat loads, while guaranteeing rapid qubit control and readout. We review design criteria for qubit drive lines, flux lines, and output lines used in typical experiments with superconducting circuits and describe each type of line in detail. The passive heat load of stainless steel and NbTi coaxial cables and the active load due to signal dissi…
Quantum computers require interfaces with classical electronics for efficient qubit control, measurement and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offer potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-transistor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large scale circui…
Continuing advancements in quantum information processing have caused a paradigm shift from research mainly focused on testing the reality of quantum mechanics to engineering qubit devices with numbers required for practical quantum computation. One of the major challenges in scaling toward large-scale solid-state systems is the limited input/output (I/O) connectors present in cryostats operating at sub-kelvin temperatures required to execute quantum logic with high-fidelity. This interconnect bottleneck is equally present in the device fabrication-measurement cycle, which requires high-throug…
Using a fully automated cryogenic wafer prober, we measured superconductor fabrication process control monitors and simple integrated circuits on 200 mm wafers at 4.4 K, including SQIF-based magnetic field sensors, SQUID-based circuits for measuring inductors, Nb/Al-AlOx/Nb Josephson junctions, test structures for measuring critical current of superconducting wires and vias, resistors, etc., to demonstrate the feasibility of using the system for characterizing niobium superconducting devices and integrated circuits on a wafer scale. Data on the wafer-scale distributions of the residual magneti…
Hyperdoping with gallium (Ga) has been established as a route to observe superconductivity in silicon (Si). The relatively large critical temperatures (T$_{\rm c}$) and magnetic fields (B$_{\rm c}$) make this phase attractive for cryogenic circuit applications, particularly for scalable hybrid superconductor--semiconductor platforms. However, the robustness of Si:Ga superconductivity at millikelvin temperatures is yet to be evaluated. Here, we report the presence of a reentrant resistive transition below T$_{\rm c}$ for Si:Ga whose strength strongly depends on the distribution of the Ga cluste…
Schottky Barrier (SB)-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a novel device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabr…
A scaled-up quantum computer will require a highly efficient control interface that autonomously manipulates and reads out large numbers of qubits, which for solid-state implementations are usually held at millikelvin (mK) temperatures. Advanced CMOS technology, tightly integrated with the quantum system, would be ideal for implementing such a control interface but is generally discounted on the basis of its power dissipation that leads to heating of the fragile qubits. Here, we demonstrate an ultra low power, CMOS-based quantum control platform that takes digital commands as input and generat…
Scalability from single qubit operations to multi-qubit circuits for quantum information processing requires architecture-specific implementations. Semiconductor hybrid qubit architecture is a suitable candidate to realize large scale quantum information processing, as it combines a universal set of logic gates with fast and all-electrical manipulation of qubits. We propose an implementation of hybrid qubits, based on Si Metal-Oxide-Semiconductor (MOS) quantum dots, compatible with the CMOS industrial technologic standards. We discuss the realization of multi-qubit circuits capable of fault-to…
Quantum computing technology is maturing at a relentless pace, yet individual quantum bits are wired one by one. As quantum processors become more complex, they require efficient interfaces to deliver signals for control and readout while keeping the number of inputs manageable. Digital electronics offers solutions to the scaling challenge by leveraging established industrial infrastructure and applying it to integrate silicon-based quantum devices with conventional CMOS circuits. Here, we combine both technologies at milikelvin temperatures and demonstrate the building blocks of a dynamic ran…
In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry…
We propose a new type of cryogenic current amplifiers, in which low-frequency power spectrum of current can be measured through a measurement of microwave response of a superconducting resonant circuit shunted by a series array of Josephson junctions. From numerical analysis on the equivalent circuit, the numerical value of the input-referred current noise of the proposed amplifier is found to be two orders of magnitude lower than the noise floor measured with the conventional cryogenic current amplifiers based on high-electron-mobility transistors or superconducting quantum interference devic…
We review our recent efforts in building atom-scale quantum-dot cellular automata circuits on a silicon surface. Our building block consists of silicon dangling bond on a H-Si(001) surface, which has been shown to act as a quantum dot. First the fabrication, experimental imaging, and charging character of the dangling bond are discussed. We then show how precise assemblies of such dots can be created to form artificial molecules. Such complex structures can be used as systems with custom optical properties, circuit elements for quantum-dot cellular automata, and quantum computing. Consideratio…
We present a novel hybrid CMOS-MQCA architecture using multi-layer Spintronic devices as computing elements. A feasibility study is presented with 22nm CMOS where new approaches for spin transfer torque induced clocking and read-out scheme for variability-tolerance are introduced. A first-of-its-kind Spintronic device model enables circuit simulation using existing CAD infrastructure. Approximately 70% reduction in energy consumption is observed when compared against conventional field-induced clocking scheme.
