Process-related and stress-induced changes in threshold voltage are major variability concerns in ultra-scaled CMOS transistors. The device designers consider this variability as an irreducible part of the design problem and use different circuit level optimization schemes to handle these variations. In this paper, we demonstrate how an increase in the negative steepness of the universal mobility relationship improves both the process-related (e.g., oxide thickness fluctuation, gate work-function fluctuation), as well as stress-induced or reliability-related (e.g., Bias Temperature Instability or BTI) parametric variation in CMOS technology. Therefore, we calibrate the universal mobility parameters to reflect the measured variation of negative steepness in uniaxially strained CMOS transistor. This allows us to study the extent of (process-related and stress-induced parametric) variation resilience in uniaxial strain technology by increasing the negative steepness of the mobility characteristics. Thus, we show that variability analysis in strained CMOS technology must consider the presence of self-compensation between mobility variation and threshold voltage variation, which leads to considerable amount of variation resilience. Finally, we use detailed circuit simulation to stress the importance of accurate mobility variation modeling in SPICE analysis and explain why the variability concerns in strained technology may be less severe than those in unstrained technology.
By means of catalytic chemical vapor deposition (CCVD) in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate without the need to transfer graphene layers. In-situ grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios. In contrast, BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1E7. The complete fabrication process is silicon CMOS compatible. This will allow a simple and low-cost in…
We explore phonon-mediated quantum transport through electronic noise characterization of a commercial CMOS transistor. The device behaves as a single electron transistor thanks to a single impurity atom in the channel. A low noise cryogenic CMOS transimpedance amplifier is exploited to perform low-frequency noise characterization down to the single electron, single donor and single phonon regime simultaneously, not otherwise visible through standard stability diagrams. Single electron tunneling as well as phonon-mediated features emerges in rms-noise measurements. Phonons are emitted at high …
We report on DC and microwave electrical transport measurements in silicon-on-insulator CMOS nano-transistors at low and room temperature. At low source-drain voltage, the DC current and RF response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature is accurately fitted by a thermionic model. From the fits…
A split gate technique is used to form a lateral quantum dot in a two-dimensional electron gas of a modulation-doped silicon/silicon-germanium heterostructure. e-beam lithography was employed to produce split gates. By applying negative voltages to these gates the underlying electron gas is depleted and a lateral quantum dot is formed, the size of which can be adjusted by the gate voltage. We observe single-electron operation with Coulomb blockade behavior below 1K. Gate leakage currents are well controlled, indicating that the recently encountered problems with Schottky gates for this type of…
In this work, Dirac fermions have been obtained and engineered in one-dimensional (1D) zigzag phosphorus nanotubes (ZPNTs). We have performed a comprehensive first-principle computational study of the electronic properties of ZPNTs with various diameters. The results indicate that as the lattice parameter (Lc) along axial direction increases, ZPNTs undergo transitions from metal to semimetal and semimetal to semiconductor, whereas Dirac fermions appear at Lc ranging from 3.90Å to 4.10Å. In particular, a field effect transistor (FET) based on a 12-ZPNT (with 12 unit cells in transverse directio…
We present an empirical model for the nearballistic transport in carbon nanotube (CNT) transistors used as strain sensors. This model describes the intrinsic effect of strain on the transport in CNTs by taking into account phonon scattering and thermally activated charge carriers. As this model relies on a semiempirical description of the electronic bands, different levels of electronic structure calculations can be used as input. The results show that the electronic structure of strained single-walled CNTs with a radius larger than 0.7nm can be described by a fully analytical model in the sen…
Single-electron transistors (SETs) have been extensively used as charge sensors in many areas such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal-oxide semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge these signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated C…
In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design…
We report strategies of achieving both high assembly yield of carbon nanotubes at selected position of the circuit via dielectrophoresis (DEP) and field effect transistor (FET) yield using semiconducting enriched single walled carbon nanotube (s-SWNT) aqueous solution. When the DEP parameters were optimized for the assembly of individual s-SWNT, 97% of the devices show FET behavior with a maximum mobility of 210 cm2/Vs, on-off current ratio ~ 106 and on conductance up to 3 μS, however with an assembly yield of only 33%. As the DEP parameters were optimized so that 1-5 s-SWNTs are connected per…
In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying…
Quantum computers require interfaces with classical electronics for efficient qubit control, measurement and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offer potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-transistor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large scale circui…
Temperature is a fundamental parameter in the study of physical phenomena. At the nanoscale, local temperature differences can be harnessed to design novel thermal nanoelectronic devices or test quantum thermodynamical concepts. Determining temperature locally is hence of particular relevance. Here, we present a primary electron thermometer that allows probing the local temperature of a single electron reservoir in single-electron devices. The thermometer is based on cyclic electron tunneling between a system with discrete energy levels and a single electron reservoir. When driven at a finite …
Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of good electrostatic control together with a high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10 nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge or III-V and dimensional scaling is expected to end around 12 nm gate-length. We demonstrate that u…
Silicon-On-Insulator nanowire transistors of very small dimensions exhibit quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for larger dimensions, allowing to design integrated circuits. Using the same process, we have co-integrated a FET-based ring oscillator circuit operating at cryogenic temperature which generates a radio-frequency (RF) signal on the gate of a nanoscale device showing Coulomb oscillations. We observe rectification of the RF signal, in good agreement with modeling.
For nanoscale CMOS applications, strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance and compatibility with conventional silicon processing. In this work, an analytical model for the output current characteristics (I-V) of nanoscale bulk strained-Si/SiGe MOSFETs, suitable for analog circuit simulation, is developed. We demonstrate significant current enhancement due to strain, even in short channel devices, attributed to the velocity overshoot effect. The accuracy of the results obtained using our analytical model is ver…
One consequence of the continued downwards scaling of transistors is the reliance on only a few discrete atoms to dope the channel, and random fluctuations of the number of these dopants is already a major issue in the microelectonics industry. While single-dopant signatures have been observed at low temperature, studying the impact of only one dopant up to room temperature requires extremely small lengths. Here, we show that a single arsenic dopant dramatically affects the off-state behavior of an advanced microelectronics field effect transistor (FET) at room temperature. Furthermore, the io…
Spin-based logic devices could operate at very high speed with very low energy consumption and hold significant promise for quantum information processing and metrology. Here, an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with a Bloch equation model using a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings is developed and applied to a spin field effect transistor (spinFET) operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a \SI{25}{nm}…
A fresh look on carbon-based transistor channel materials like single-walled carbon nanotubes (CNT) and graphene nanoribbons (GNR) in future electronic applications is given. Although theoretical predictions initially promised that GNR (which do have a bandgap) would perform equally well as transistors based on CNTs, experimental evidence for the well-behaved transistor action is missing up to now. Possible reasons for the shortcomings as well as possible solutions to overcome the performance gap will be addressed. In contrast to GNR, short channel CNT field effect transistors (FET) demonstrat…
We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 $\times$ 20 nm$^{2}$ is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement…
We describe the fundamental trade-offs in engineering the mobility, current saturation and ON- OFF ratios in graphene transistors. Surprisingly, the trade-offs arise solely from an asymptotic constraint on the high energy bandstructure and independent of scattering processes. This places graphite derivatives (bulk monolayer graphene, uniaxially strained graphene nanoribbons, carbon nanotubes and bilayer graphene) on the same 3-parameter mobility-bandgap-scattering length (μ - Egap -λ) plot, proximal to other semiconductors. In addition to this low-bias trade-off, the high bias current bears si…
In 1963, Moll and Tarui suggested that the field-effect conductance of a semiconductor could be controlled by the remanent polarization of a ferroelectric (FE) material to create a ferroelectric field-effect transistor (FE-FET). However, subsequent efforts to produce a practical, compact FE-FET have been plagued by low retention and incompatibility with Complementary Metal Oxide Semiconductor (CMOS) process integration. These difficulties led to the development of trapped-charge based memory devices (also called floating gate or flash memory), and these are now the mainstream non-volatile memo…
Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as tunnelling and coherence, can be harnessed to use existing CMOS technology for quantum information processing. Here, we report the observation of coherent charge oscillations in a double quantum dot formed in a silicon nanowire transistor detected via its dispersive interaction with a radio-frequency resonant circuit coupled via the gate. Differential capacitan…
In this paper we propose two transistor concepts based on lateral heterostructures of monolayer MoS$_2$, composed of adjacent regions of 1T (metallic) and 2H (semiconducting) phases, inspired by recent research showing the possibility to obtain such heterostructures by electron beam irradiation. The first concept, the lateral heterostructure field-effect transistor, exhibits potential of better performance with respect to the foreseen evolution of CMOS technology, both for high performance and low power applications. Performance potential has been evaluated by means of detailed multi-scale mat…
Tunnel Field Effect Transistors (TFET) have extremely low leakage current, exhibit excellent subthreshold swing and are less susceptible to short channel effects. However, TFETs do face certain special challenges, particularly with respect to the process induced variations in (i) the channel length and (ii) the thickness of the silicon thin-film and the gate oxide. This paper, for the first time, studies the impact of the above process variations on the electrical characteristics of a Double Gate Tunnel Field Effect Transistor (DGTFET). Using two dimensional device simulations, we propose the …
Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at temperatures ranging from 300K down to 4.2K. We extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. In addition to their I-V characteristics, threshold voltage(Vth) values, on/off current ratio, transconductance of the MOS transistors, and resistors on chips are measured at temperatures from 300K down to …
In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establ…
We demonstrate that a lightly-strained germanium channel ($\varepsilon_{//}$ = -0.41%) in an undoped Ge/Si$_{0.1}$Ge$_{0.9}$ heterostructure field effect transistor supports a 2D hole gas with mobility in excess of 1$\times$10$^{6}$ cm$^{2}$/Vs and percolation density less than 5$\times$10$^{10}$ cm$^{-2}$. This low disorder 2D hole system shows tunable fractional quantum Hall effect at low density and low magnetic field. The low-disorder and small effective mass (0.068$m_e$) defines lightly-strained germanium as a basis to tune the strength of the spin-orbit coupling for fast and coherent qua…
We invented a novel method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. By means of catalytic chemical vapor deposition (CCVD) the in-situ grown bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g. temperature and gas mixture. BiLGFETs exhibit ultra-high on/off-current ratios of 107 at room temperature, exceeding previously reported values by several orders of magnitude. This will allow a …
We numerically investigate the possibility of using Tunnel field-effect transistor (TFET) in a 32 kHz crystal oscillator circuit to reduce power consumption. A simulation using SPICE (Simulation Program with Integrated Circuit Emphasis) is carried out based on a conventional CMOS transistor model. It is shown that the power consumption of TFET is one-tenth that of conventional low-power CMOS.
The inter-device mismatch and intra-device temporal instability in the nanoscale CMOS circuits is examined from a unified point of view as a static and dynamic parts of the variability con-cerned with stochastic oxide charge trapping and de-trapping. This approach has been benchmarked on the recent evidence of the radiation-induced increase of inter-transistor mismatch in 60 nm ICs. A possible reliability limitation in ultrascale circuits concerned with the single or a few charged defect instability is pointed out and estimated.
CMOS + stochastic nanomagnets: heterogeneous computers for probabilistic inference and learning
University of California Santa Barbara（加州大学圣巴巴拉分校）；Tohoku University（东北大学）；Research Institute of Electrical Communication, Tohoku University（东北大学电气通信研究所）；Graduate School of Engineering, Tohoku University（东北大学工学研究科）
In this work, double-gated field effect transistors manufactured from monolayer graphene are investigated. Conventional top-down CMOS-compatible processes are applied except for graphene deposition by manual exfoliation. Carrier mobilities in single- and double gated graphene field effect transistors are compared. Even in double-gated graphene FETs, the carrier mobility exceeds the universal mobility of silicon over nearly the entire measured range. At comparable dimensions, reported mobilities for ultra thin body silicon-on-insulator MOSFETs can not compete with graphene FET values.
The integration of efficient, miniaturized group IV lasers into CMOS architecture holds the key to the realization of fully functional photonic-integrated circuits. Despite several years of progress, however, all group IV lasers reported to date exhibit impractically high thresholds owing to their unfavorable bandstructures. Highly strained germanium with its fundamentally altered bandstructure has emerged as a potential low-threshold gain medium, but there has yet to be any successful demonstration of lasing from this seemingly promising material system. Here, we demonstrate a low-threshold, …
Intimate integration of memory devices with logic transistors is a frontier challenge in computer hardware. This integration is essential for augmenting computational power concurrently with enhanced energy efficiency in big-data applications such as artificial intelligence. Despite decades of efforts, reliable, compact, energy efficient and scalable memory devices are elusive. Ferroelectric Field Effect Transistors (FE-FETs) are a promising candidate but their scalability and performance in a back-end-of-line (BEOL) process remain unattained. Here, we present scalable BEOL compatible FE-FETs …
Nano-electronic integrated circuit technology is exclusively based on MOSFET transistor due to its scalability down to the nanometer range. On the other hand, Bipolar Junction Transistor (BJT), which provides unmatched analog characteristics and frequency response, cannot be scaled to nanometer regime without the loss of transistor action. Here a versatile nanoscale transistor is introduced that provides identical BJT behavior and expands its capabilities. The new transistor uses CMOS fabrication technology and creates BJT emitter, base, and collector via electric fields. By allowing carrier m…
We fabricate an undoped Ge quantum well under 30 nm Ge0.8Si0.2 shallow barrier with reverse grading technology. The under barrier is deposited by Ge0.8Si0.2 followed by Ge0.9Si0.1 so that the variation of Ge content forms a sharp interface which can suppress the threading dislocation density penetrating into undoped Ge quantum well. And the Ge0.8Si0.2 barrier introduces enough in-plane parallel strain -0.41% in the Ge quantum well. The heterostructure field-effect transistors with a shallow buried channel get a high two-dimensional hole gas (2DHG) mobility over 2E6 cm2/Vs at a low percolation …
Quantum computing technology is maturing at a relentless pace, yet individual quantum bits are wired one by one. As quantum processors become more complex, they require efficient interfaces to deliver signals for control and readout while keeping the number of inputs manageable. Digital electronics offers solutions to the scaling challenge by leveraging established industrial infrastructure and applying it to integrate silicon-based quantum devices with conventional CMOS circuits. Here, we combine both technologies at milikelvin temperatures and demonstrate the building blocks of a dynamic ran…
