We report strategies of achieving both high assembly yield of carbon nanotubes at selected position of the circuit via dielectrophoresis (DEP) and field effect transistor (FET) yield using semiconducting enriched single walled carbon nanotube (s-SWNT) aqueous solution. When the DEP parameters were optimized for the assembly of individual s-SWNT, 97% of the devices show FET behavior with a maximum mobility of 210 cm2/Vs, on-off current ratio ~ 106 and on conductance up to 3 μS, however with an assembly yield of only 33%. As the DEP parameters were optimized so that 1-5 s-SWNTs are connected per electrode pair, the assembly yield was almost 90% with ~ 90% of these assembled devices demonstrating FET behavior. Further optimization gives an assembly yield of 100% with up to 10 SWNT/site, however with a reduced FET yield of 59%. Improved FET performance including higher current on-off ratio and high switching speed were obtained by integrating a local Al2O3 gate to the device. Our 90% FET with 90% assembly yield is the highest reported so far for carbon nanotube devices. Our study provides a pathway which could become a general approach for the high yield fabrication of CMOS compatible carbon nanotube FETs.
By means of catalytic chemical vapor deposition (CCVD) in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate without the need to transfer graphene layers. In-situ grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios. In contrast, BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1E7. The complete fabrication process is silicon CMOS compatible. This will allow a simple and low-cost in…
Sub-10nm wide graphene nanoribbon field-effect transistors (GNRFETs) are studied systematically. All sub-10nm GNRs afforded semiconducting FETs without exception, with Ion/Ioff ratio up to 10^6 and on-state current density as high as ~2000uA/um. We estimated carrier mobility ~200cm2/Vs and scattering mean free path ~10nm in sub-10nm GNRs. Scattering mechanisms by edges, acoustic phonon and defects are discussed. The sub-10nm GNRFETs are comparable to small diameter (d<=~1.2nm) carbon nanotube FETs with Pd contacts in on-state current density and Ion/Ioff ratio, but have the advantage of produc…
We explore phonon-mediated quantum transport through electronic noise characterization of a commercial CMOS transistor. The device behaves as a single electron transistor thanks to a single impurity atom in the channel. A low noise cryogenic CMOS transimpedance amplifier is exploited to perform low-frequency noise characterization down to the single electron, single donor and single phonon regime simultaneously, not otherwise visible through standard stability diagrams. Single electron tunneling as well as phonon-mediated features emerges in rms-noise measurements. Phonons are emitted at high …
We report on DC and microwave electrical transport measurements in silicon-on-insulator CMOS nano-transistors at low and room temperature. At low source-drain voltage, the DC current and RF response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature is accurately fitted by a thermionic model. From the fits…
Process-related and stress-induced changes in threshold voltage are major variability concerns in ultra-scaled CMOS transistors. The device designers consider this variability as an irreducible part of the design problem and use different circuit level optimization schemes to handle these variations. In this paper, we demonstrate how an increase in the negative steepness of the universal mobility relationship improves both the process-related (e.g., oxide thickness fluctuation, gate work-function fluctuation), as well as stress-induced or reliability-related (e.g., Bias Temperature Instability…
Single-electron transistors (SETs) have been extensively used as charge sensors in many areas such as quantum computations. In general, the signals of SETs are smaller than those of complementary metal-oxide semiconductor (CMOS) devices, and many amplifying circuits are required to enlarge these signals. Instead of amplifying a single small output, we theoretically consider the amplification of pairs of SETs, such that one of the SETs is used as a reference. We simulate the two-stage amplification process of SETs and CMOS devices using a conventional SPICE (Simulation Program with Integrated C…
High-performance solution-processed short-channel carbon nanotube (CNT) thin film transistors (TFTs) are fabricated using densely aligned arrays of metallic CNTs (m-CNTs) as source and drain electrodes, and aligned arrays of semiconducting enriched CNTs (s-CNTs) as channel material. The electrical transport measurements at room temperature show that the m-CNT contacted s-CNT array devices with a 2 um channel length perform superiorly to those of control Pd contacted s-CNT devices. The m-CNT contacted devices exhibit a maximum (average) on-conductance of 36.5 uS (19.2 uS), transconductance of 2…
In this paper, we demonstrate by simulation the feasibility of electrostatically doped and therefore reconfigurable planar field-effect-transistor (FET) structure which is based on our already fabricated and published Si-nanowire (SiNW) devices. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable on the fly by applying an appropriate control-gate voltage which significantly increases the versatility and flexibility in the design…
We use a simultaneous flow of ethylene and hydrogen gases to grow single wall carbon nanotubes by chemical vapor deposition. Strong coupling to the gate is inferred from transport measurements for both metallic and semiconducting tubes. At low-temperatures, our samples act as single-electron transistors where the transport mechanism is mainly governed by Coulomb blockade. The measurements reveal very rich quantized energy level spectra spanning from valence to conduction band. The Coulomb diamonds have similar addition energies on both sides of the semiconducting gap. Signatures of subbands po…
We investigate electronic transport properties of Schottky-barrier field-effect transistors (FET) based on double-walled carbon nanotubes (DWNT) with a semiconducting outer shell and a metallic inner one. These kind of DWNT-FET show asymmetries of the $I$-$V$ characteristics and threshold voltages due to the electron-hole asymmetry of the Schottky barrier. The presence of the metallic inner shell induces a large effective band gap, which is one order of magnitude larger than that due to the semiconducting shell alone of a single-walled carbon nanotube FET.
In this paper, we demonstrate by simulation the general usability of an electrostatically doped and electrically reconfigurable planar field-effect transistor (FET) structure. The device concept is partly based on our already published and fabricated silicon nanowire 3D-FET technology. The technological key features of this general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) substrate additionally enabling high-temperature operation of the proposed device. The transistors charge carrier type, i.e. n- or ptype FET, is electrically switchable on the fly by applying…
In this paper we propose two transistor concepts based on lateral heterostructures of monolayer MoS$_2$, composed of adjacent regions of 1T (metallic) and 2H (semiconducting) phases, inspired by recent research showing the possibility to obtain such heterostructures by electron beam irradiation. The first concept, the lateral heterostructure field-effect transistor, exhibits potential of better performance with respect to the foreseen evolution of CMOS technology, both for high performance and low power applications. Performance potential has been evaluated by means of detailed multi-scale mat…
Quantum computers require interfaces with classical electronics for efficient qubit control, measurement and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offer potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-transistor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large scale circui…
Temperature is a fundamental parameter in the study of physical phenomena. At the nanoscale, local temperature differences can be harnessed to design novel thermal nanoelectronic devices or test quantum thermodynamical concepts. Determining temperature locally is hence of particular relevance. Here, we present a primary electron thermometer that allows probing the local temperature of a single electron reservoir in single-electron devices. The thermometer is based on cyclic electron tunneling between a system with discrete energy levels and a single electron reservoir. When driven at a finite …
Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10 nm scaling for high-performance CMOS applications. We show that a combination of good electrostatic control together with a high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10 nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge or III-V and dimensional scaling is expected to end around 12 nm gate-length. We demonstrate that u…
Nanocomposites of ferrocenyl-modified gold clusters and semiconducting polymers that integrate field-effect transistor and flash memory in a single neuromorphic device
Silicon-On-Insulator nanowire transistors of very small dimensions exhibit quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for larger dimensions, allowing to design integrated circuits. Using the same process, we have co-integrated a FET-based ring oscillator circuit operating at cryogenic temperature which generates a radio-frequency (RF) signal on the gate of a nanoscale device showing Coulomb oscillations. We observe rectification of the RF signal, in good agreement with modeling.
One consequence of the continued downwards scaling of transistors is the reliance on only a few discrete atoms to dope the channel, and random fluctuations of the number of these dopants is already a major issue in the microelectonics industry. While single-dopant signatures have been observed at low temperature, studying the impact of only one dopant up to room temperature requires extremely small lengths. Here, we show that a single arsenic dopant dramatically affects the off-state behavior of an advanced microelectronics field effect transistor (FET) at room temperature. Furthermore, the io…
A fresh look on carbon-based transistor channel materials like single-walled carbon nanotubes (CNT) and graphene nanoribbons (GNR) in future electronic applications is given. Although theoretical predictions initially promised that GNR (which do have a bandgap) would perform equally well as transistors based on CNTs, experimental evidence for the well-behaved transistor action is missing up to now. Possible reasons for the shortcomings as well as possible solutions to overcome the performance gap will be addressed. In contrast to GNR, short channel CNT field effect transistors (FET) demonstrat…
We report on a new computational model to efficiently simulate carbon nanotubebased field effect transistors (CNT-FET). In the model, a central region is formed by a semiconducting nanotube that acts as the conducting channel, surrounded by a thin oxide layer and a metal gate electrode. At both ends of the semiconducting channel, two semi-infinite metallic reservoirs act as source and drain contacts. The current-voltage characteristics are computed using the Landauer formalism, including the effect of the Schottky barrier physics. The main operational regimes of the CNT-FET are described, incl…
We report electronic transport on n-type silicon Single Electron Transistors (SETs) fabricated in Complementary Metal Oxide Semiconductor (CMOS) technology. The n-MOSSETs are built within a pre-industrial Fully Depleted Silicon On Insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 $\times$ 20 nm$^{2}$ is obtained by employing electron beam lithography for active and gate levels patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement…
We present electrical data of silicon single electron devices fabricated with CMOS techniques and protocols. The easily tuned devices show clean Coulomb diamonds at T = 30 mK and charge offset drift of 0.01 e over eight days. In addition, the devices exhibit robust transistor characteristics including uniformity within about 0.5 V in the threshold voltage, gate resistances greater than 10 GΩ, and immunity to dielectric breakdown in electric fields as high as 4 MV/cm. These results highlight the benefits in device performance of a fully CMOS process for single electron device fabrication.
We investigate theoretically the switching characteristics of semiconducting carbon nanotubes connected to gold electrodes under an external (gate) electric field. We find that the external introduction of holes is necessary to account for the experimental observations. We identify metal-induced-gap states (MIGS) at the contacts and find that the MIGS of an undoped tube would not significantly affect the switching behavior, even for very short tube lengths. We also explore the miniaturization limits of nanotube transistors, and, on the basis of their switching ratio, we conclude that transisto…
In 1963, Moll and Tarui suggested that the field-effect conductance of a semiconductor could be controlled by the remanent polarization of a ferroelectric (FE) material to create a ferroelectric field-effect transistor (FE-FET). However, subsequent efforts to produce a practical, compact FE-FET have been plagued by low retention and incompatibility with Complementary Metal Oxide Semiconductor (CMOS) process integration. These difficulties led to the development of trapped-charge based memory devices (also called floating gate or flash memory), and these are now the mainstream non-volatile memo…
The 1/f noise in individual semiconducting carbon nanotubes (s-CNT) in a field effect transistor configuration has been measured in ultra-high vacuum and following exposure to air. The amplitude of the normalized current spectral noise density is independent of source-drain current, indicating the noise is due to mobility rather than number fluctuations. Hooge's constant for s-CNT is found to be 9.3 plus minus 0.4x10^-3. The magnitude of the 1/f noise is substantially degreased by exposing the devices to air.
Quantum mechanical effects induced by the miniaturization of complementary metal-oxide-semiconductor (CMOS) technology hamper the performance and scalability prospects of field-effect transistors. However, those quantum effects, such as tunnelling and coherence, can be harnessed to use existing CMOS technology for quantum information processing. Here, we report the observation of coherent charge oscillations in a double quantum dot formed in a silicon nanowire transistor detected via its dispersive interaction with a radio-frequency resonant circuit coupled via the gate. Differential capacitan…
We report the transport properties of mechanically exfoliated few-layer SnSe$_{2}$ flakes, whose mobility is found with four probe measurements to be ~ 85 cm$^{2}$V$^{-1}$s$^{-1}$ at 300 K, higher than those of the majority of few-layer transitional metal dichalcogenides (TMDs). The mobility increases strongly with decreased temperature, indicating a phonon limited transport. The conductivity of the semiconducting SnSe$_{2}$ shows a metallic behavior, which is explained by two competing factors involving the different temperature dependence of mobility and carrier density. The Fermi level is f…
In the past decade, semiconducting carbon nanotube thin films have been recognized as contending materials for wide-ranging applications in electronics, energy, and sensing. In particular, improvements in large-area flexible electronics have been achieved through independent advances in post-growth processing to resolve metallic versus semiconducting carbon nanotube heterogeneity, in improved gate dielectrics, and in self-assembly processes. Moreover, controlled tuning of specific device components has afforded fundamental probes of the trade-offs between materials properties and device perfor…
Atomically-thin 2D semiconducting materials integrated into van der Waals heterostructures have enabled architectures that hold great promise for next generation nanoelectronics. However, challenges still remain to enable their full acceptance as compliant materials for integration in logic devices. Two key-components to master are the barriers at metal/semiconductor interfaces and the mobility of the semiconducting channel, which endow the building-blocks of ${pn}$ diode and field effect transistor. Here, we have devised a reverted stacking technique to intercalate a wrinkle-free h-BN tunnel …
Recent experiments shown that graphene epitaxially grown on Silicon Carbide (SiC) can exhibit a energy gap of 0.26 eV, making it a promising material for electronics. With an accurate model, we explore the design parameter space for a fully ballistic graphene-on-SiC Tunnel Field-Effect Transistors (TFETs), and assess the DC and high frequency figures of merit. The steep subthreshold behavior can enable I_{ON}/I_{OFF} ratios exceeding 10^4 even with a low supply voltage of 0.15 V, for devices with gatelength down to 30 nm. Intrinsic transistor delays smaller than 1 ps are obtained. These factor…
We report on fabrication of single-electron transistors using InAs nanowires with epitaxial aluminium with fixed tunnel barriers made of aluminium oxide. The devices exhibit a hard superconducting gap induced by the proximized aluminium cover shell and they behave as metallic single-electron transistors. In contrast to the typical few channel contacts in semiconducting devices, our approach forms opaque multichannel contacts to a semiconducting wire and thus provides a complementary way to study them. In addition, we confirm that unwanted extra quantum dots can appear at the surface of the nan…
We have investigated shot noise in a 6-nm-diameter, semiconducting multiwalled carbon nanotube FET at 4.2 K over the frequency range 600 - 950 MHz. We find a transconductance of 3 - 3.5 $μ$S for optimal positive and negative source-drain voltages V. For the gate referred input voltage noise, we obtain 0.2 and 0.3 $μ{V}/ \sqrt{Hz}$ for V>0 and V<0, respectively. As effective charge noise this corresponds to $2-3 \cdot 10^{-5}$ e/$\sqrt{Hz}$.
Carbon nanotube field-effect transistors (FETs) with passivated coaxial gate structures have been fabricated after growth of contacted suspended single wall nanotubes (SWNTs) and subsequent coating with gate dielectrics. Electron Fabry-Perot interferences are observed in the FETs indicating ballistic transport in the coated structures. Reliable production of high-performance SWNT FETs has been obtained by combining patterned growth of SWNT arrays with feed-back controlled electrical breakdown to select desired semiconducting SWNTs, making large-scale SWNT FET fabrication achievable. P-type and…
Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at temperatures ranging from 300K down to 4.2K. We extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. In addition to their I-V characteristics, threshold voltage(Vth) values, on/off current ratio, transconductance of the MOS transistors, and resistors on chips are measured at temperatures from 300K down to …
We report a numerical study of the tunnel conductance through the Schottky barrier at the contact between a semiconducting carbon nanotube and a metal electrode. In a planar gate model the asymmetry between the p--doped and the n--doped region is shown to depend mainly on the difference between the electrode Fermi level and the band gap of carbon nanotubes. We quantitatively show how the gate/nanotube distance is important to get large on--off ratios. We explain the bend of the current versus gate voltage as the transition from a thermal--activation region to a tunneling region. A good agreeme…
Single-walled carbon nanotubes (SWNTs) have been grown via chemical vapor deposition on high-kappa dielectric SrTiO3/Si substrates, and high-performance semiconducting SWNT field-effect transistors have been fabricated using the thin SrTiO3 as gate dielectric and Si as gate electrode. The transconductance per channel width is 8900 S/m. The high transconductance cannot be explained by the increased gate capacitance; it is proposed that the increased electric field at the nanotube-electrode interface due to the high-kappa SrTiO3 decreases or eliminates the nanotube-electrode Schottky barrier.
Spectroscopic, time-resolved scanning photocurrent microscopy is shown to distinguish the intrinsic photoresponse of monodisperse semiconducting (99%) single-walled carbon nanotubes (SWCNTs) from the extrinsic photoresponse of the substrate. A persistent positive photocurrent induced by near-IR excitation is attributed to the generation of free carriers by inter-band excitation in SWCNTs. For shorter excitation wavelengths, absorption by the Si substrate generates two types of photocurrent: a transient positive photoresponse, identified as a displacement current, and a persistent negative phot…
High performance enhancement mode semiconducting carbon nanotube field-effect transistors (CNTFETs) are obtained by combining ohmic metal-tube contacts, high dielectric constant HfO2 films as gate insulators, and electrostatically doped nanotube segments as source/drain electrodes. The combination of these elements affords high ON currents, subthreshold swings of ~ 70-80 mV/decade, and allows for low OFF currents and suppressed ambipolar conduction. The doped source and drain approach resembles that of MOSFETs and can impart excellent OFF states to nanotube FETs under aggressive vertical scali…
We investigate the role of various structural nonidealities on the performance of armchair-edge graphene nanoribbon field effect transistors (GNRFETs). Our results show that edge roughness dilutes the chirality dependence often predicted by theory but absent experimentally. Instead, GNRs are classifiable into wide (semi-metallic) vs narrow (semiconducting) strips, defining thereby the building blocks for wide-narrow-wide all-graphene devices and interconnects. Small bandgaps limit drain bias at the expense of band-to-band tunneling in GNRFETs. We outline the relation between device performance…
Semiconducting two-dimensional (2D) transition metal dichalcogenides (TMDs) are emerging as top candidates for post-silicon electronics. While most of 2D TMDs exhibit isotropic behavior, lowering the lattice symmetry could induce anisotropic properties, which are both scientifically interesting and potentially useful. Here, we present atomically thin rhenium disulfide (ReS2) flakes with a unique distorted 1T structure, which exhibit in-plane anisotropic properties. We fabricated mono- and few-layer ReS2 field effect transistors (FETs), which exhibit competitive performance with large current o…
In this paper, we present experimental results and simulation data of an electrostatically doped and therefore voltage-programmable, planar, CMOS-compatible field-effect transistor (FET) structure. This planar device is based on our previously published Si-nanowire (SiNW) technology. Schottky barrier source/drain (S/D) contacts and a silicon-on-insulator (SOI) technology platform are the key features of this dual-gated but single channel universal FET. The combination of two electrically independent gates, one back-gate for S/D Schottky barrier modulation as well as channel formation to establ…
Silicon quantum dots are attractive candidates for the development of scalable, spin-based qubits. Pauli spin blockade in double quantum dots provides an efficient, temperature independent mechanism for qubit readout. Here we report on transport experiments in double gate nanowire transistors issued from a CMOS process on 300 mm silicon-on-insulator wafers. At low temperature the devices behave as two few-electron quantum dots in series. We observe signatures of Pauli spin blockade with a singlet-triplet splitting ranging from 0.3 to 1.3 meV. Magneto-transport measurements show that transition…
We demonstrate the realization of an electrically-driven integrated source of surface plasmon polaritons. Light-emitting individual single-walled carbon nanotube field effect transistors were fabricated in a plasmonic-ready platform. The devices were operated at ambient condition to act as an electroluminescence source localized near the contacting gold electrodes. We show that photon emission from the semiconducting channel can couple to propagating surface plasmons developing in the electrical terminals. Momentum-space spectroscopy suggests that excited plasmon modes are bound to the metal-g…
We report an experimental noise study of intermediate sized quasi ballistic semiconducting multiwalled carbon nanotube (IS-MWCNT) devices. The noise is two orders of magnitude lower than in singlewalled nanotubes (SWCNTs) and has no length dependence within the studied range. In these channel limited devices with small or negligible Schottky barriers the noise is shown to originate from the intrinsic potential fluctuations of charge traps in the gate dielectric. The gate dependence of normalized noise can be explained better using ballistic the charge noise model rather than diffusive McWhorte…
We numerically investigate the possibility of using Tunnel field-effect transistor (TFET) in a 32 kHz crystal oscillator circuit to reduce power consumption. A simulation using SPICE (Simulation Program with Integrated Circuit Emphasis) is carried out based on a conventional CMOS transistor model. It is shown that the power consumption of TFET is one-tenth that of conventional low-power CMOS.
Next-generation electronics calls for new materials beyond silicon for increased functionality, performance, and scaling in integrated circuits. Carbon nanotubes and semiconductor nanowires are at the forefront of these materials, but have challenges due to the complex fabrication techniques required for large-scale applications. Two-dimensional (2D) gapless graphene and semiconducting transition metal dichalcogenides (TMDCs) have emerged as promising electronic materials due to their atomic thickness, chemical stability and scalability. Difficulties in the assembly of 2D electronic structures…
Layered two-dimensional (2D) semiconducting transition metal dichalcogenides (TMD) have been widely isolated, synthesized, and characterized recently. Numerous 2D materials are identified as the potential candidates as channel materials for future thin film technology due to their high mobility and the exhibiting bandgaps. While many TMD filed-effect transistors (FETs) have been widely demonstrated along with a significant progress to clearly understand the device physics, large contact resistance at metal/semiconductor interface still remain a challenge. From 2D device research point of view,…
The inter-device mismatch and intra-device temporal instability in the nanoscale CMOS circuits is examined from a unified point of view as a static and dynamic parts of the variability con-cerned with stochastic oxide charge trapping and de-trapping. This approach has been benchmarked on the recent evidence of the radiation-induced increase of inter-transistor mismatch in 60 nm ICs. A possible reliability limitation in ultrascale circuits concerned with the single or a few charged defect instability is pointed out and estimated.
