Future detectors for high luminosity particle identification and ultra high energy neutrino observation would benefit from a digitizer capable of recording sensor elements with high analog bandwidth and large record depth, in a cost-effective, compact and low-power way. A first version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRADOR ASIC has been very successful and forms the basis of a generation of new, large-scale radio neutrino detectors, its limited sampling depth is a major drawback. A prototype has been designed and fabricated with 65k deep sampling at multi-GSa/s operation. We present test results and directions for future evolution of this sampling technique.
We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 degrees celsius shows negligible degradation over 16 days.
Scientific detectors are a key technological enabler for many disciplines. Application-specific integrated circuits (ASICs) are used for many of these scientific detectors. Until recently, pixel detector ASICs have been used mainly for analog signal processing of the charge from the sensor layer and the transmission of raw pixel data off the detector ASIC. However, with the availability of more advanced ASIC technology nodes for scientific application, more digital functionality from the computing domains (e.g., compression) can be integrated directly into the detector ASIC to increase data ve…
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with \b{eta}-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplifi…
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $μ$-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the S…
Front-end ASIC for Spectroscopic Readout of Virtual Frisch-Grid CZT Bar Sensors
紧凑型多通道辐射探测器依靠低噪声前端专用集成电路（ASIC）实现高光谱分辨率。在这里，一个新的ASIC开发读出虚拟弗里希栅碲锌镉（VFG CZT）探测器的γ射线光谱。对应于检测器中的每个电离事件，ASIC测量与检测器阵列中的每个传感器相关联的阳极、阴极和四个垫感测电极处的振幅和定时。ASIC由52个通道组成，其中有4个阴极通道和48个通道，这些通道可以被配置为具有250 mV基线的阳极通道或焊盘感测通道以处理具有1.2 V基线的感应信号。静态功耗为3 mW，每个通道执行低噪声电荷放大、高阶整形、峰值和定时检测以及模拟存储和多路复用。对于3 MeV范围内大于8 fC的电荷，总体通道线性度优于$\pm$ 1%，定时分辨率低至700 ps。通过连接并偏置的6 mm x 6 mm x 20 mm虚拟弗里希栅条传感器的4 x 4阵列，测量了3.2 MeV范围内高达100 fC的电荷的$\approx$ 270 rms $e^{-}$的电子分辨率。用3D校正技术获得的光谱测量结果表明，在238 keV和662 keV下的分辨率分别为1.8%FWHM和0.9%FWHM。
The continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-c…
Development and characterization of hybrid MCP-PMT with embedded Timepix4 ASIC used as pixelated anode
INFN, Division of Ferrara（意大利国家核物理研究所费拉拉分部）；Dept. of Physics and Earth Science, University of Ferrara（费拉拉大学地球科学与物理学系）；EP Department, CERN（欧洲核子研究中心实验物理部）
For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an excellent timing resolution below 50 ps. The front-end read-out ASIC must maintain the performance of the sensor, while keeping low power consumption. This paper presents the results on the first prototype of a front-end ASIC, named ALTIROC0, which contains the analog stages (preamplifier an…
PSEC6: an 8-Channel 40 GSa/s Waveform Sampling ASIC in TSMC 65nm with 10.24 GHz PLL
Enrico Fermi Institute, the University of Chicago（芝加哥大学恩里科·费米研究所）；Fermi National Accelerator Laboratory（费米国家加速器实验室）；Stanford University（斯坦福大学）；North Central College（北中央学院）
A monolithic silicon pixel detector prototype has been produced in the SiGe BiCMOS SG13G2 130 nm node technology by IHP. The ASIC contains a matrix of hexagonal pixels with pitch of approximately 100 $μ$m. Three analog pixels were calibrated in laboratory with radioactive sources and tested in a 180 GeV/c pion beamline at the CERN SPS. A detection efficiency of $\left(99.9^{+0.1}_{-0.2}\right)$% was measured together with a time resolution of $(36.4 \pm 0.8)$ps at the highest preamplifier bias current working point of 150 $μ$A and at a sensor bias voltage of 160 V. The ASIC was also characteri…
IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of 16 x 16 pixels CdTe or CdZnTe pixelated detectors to build low power micro gamma camera. IDeF-X HD has been designed in the standard AMS CMOS 0.35 microns process technology. Its power consumption is 800 micro watt per channel. The dynamic range of the ASIC can be extended to 1.1 MeV thanks to the in-channel adjustable gain stage. When no detector is connected to the chip and without input current, a 33 electrons rms ENC level is achieved after shaping with 10.7 micro seconds peak time. Spec…
Characterization of a 28 nm $\textit{smartpixels}$ ASIC With On-Chip ML for Particle Tracking Detectors
Fermi National Accelerator Laboratory（费米国家加速器实验室）；University of Illinois Chicago（伊利诺伊大学芝加哥分校）；The University of Chicago（芝加哥大学）；Northwestern University（西北大学）；Politecnico di Milano（米兰理工大学）；INFN, Sezione di Milano（意大利国家核物理研究所米兰分部）；Purdue University（普渡大学）；Cornell University（康奈尔大学）
This work presents the design of BUSARD, an application specific integrated circuit (ASIC) for the detection of ionizing particles. The ASIC is a monolithic active pixel sensor which has been fabricated in a High-Voltage Silicon-On-Insulator (HV-SOI) process that allows the fabrication of a buried N+ diffusion below the Buried OXide (BOX) as a standard processing step. The first version of the chip, BUSARD-A, takes advantage of this buried diffusion as an ionizing particle sensor. It includes a small array of 13$\times$13 pixels, with a pitch of $80\,μ$m, and each pixel has one buried diffusio…
An Application Specific Integrated Circuit (ASIC), called RIGEL, designed for the sparse readout of a Silicon Pixel Drift Detector (PixDD) for space applications is presented.The low leakage current (less than 1 pA at +20 °C) and anode capacitance (less than 40 fF) of each pixel (300 um x 300 um) of the detector, combined with a low-noise electronics readout, allow to reach a high spectroscopic resolution performance even at room temperature. The RIGEL ASIC front-end architecture is composed by a 2-D matrix of 128 readout pixel cells (RPCs), arranged to host, in a 300 um-sided square area, a c…
