15GSa/s、1.5GHz带宽的波形数字化ASIC
A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC
摘要：
PSEC4定制集成电路设计用于记录大面积飞行时间探测器系统中使用的快速波形。ASIC采用IBM-8RF 0.13微米CMOS工艺制造。在6个模拟通道中的每一个上，PSEC4采用256个样本深度的开关电容阵列（SCA）、具有10.5位DC动态范围的斜坡比较ADC以及具有感兴趣区域窗口功能的串行数据读出，以减少死区时间。所有通道的采样速率可在4至15千兆采样/秒[GSa/s]之间调整，并通过低抖动延迟锁定环（DLL）进行片内伺服控制。输入信号在片内无源耦合，-3 dB模拟带宽为1.5 GHz。静态采样模式下的功耗小于50 mW/芯片;在持续触发和读出速率为50 kHz时，芯片功耗为100 mW。在固定模式基座减法后，在750 mV动态范围内，未校正的积分非线性为0.15%。采样时基具有固定模式的非线性，RMS为13%，可进行校正，以实现精确的波形特征提取和定时。
英文摘要：
The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over an 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available.The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.
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