PSEC6：采用台积电65nm工艺的8通道40 GSa/s波形采样专用集成电路（ASIC），集成10.24 GHz锁相环（PLL）
PSEC6: an 8-Channel 40 GSa/s Waveform Sampling ASIC in TSMC 65nm with 10.24 GHz PLL
AI总结：
本文针对皮秒级定时分辨率需求，设计出台积电65nm工艺的8通道40 GSa/s波形采样ASIC PSEC6，集成65nm工艺首款10.24 GHz PLL，仿真验证了其关键性能参数，为相关物理测量提供支持。
AI中文摘要：
皮秒级定时分辨率是提升符合匹配、飞行时间测量及次级顶点重建的必要前提能力。本文介绍了采用台积电65nm工艺的新型专用集成电路（ASIC）PSEC6的规格、设计与仿真结果。该芯片具备8个通道，最大采样率为40 GSa/s，缓冲器长度为204.8纳秒，集成了10.24 GHz锁相环（PLL），这是65nm CMOS工艺中首款此类PLL。事件读出速率为32 kHz，数字化由片外模数转换器（ADC）完成。仿真预测其模拟输入带宽为4.0 GHz，采样时每通道功耗20 mW；10.24 GHz PLL的预测均方根抖动为550 fs，功耗15.7 mW。本文描述了采样架构、芯片信号路径、PLL设计，并给出了仿真结果。
英文摘要：
Picosecond level timing resolution is a prerequisite capability for improved coincidence matching, time-of-flight measurements, and secondary vertex reconstruction. Here, we present the specification, design, and simulation results for a new Application Specific Integrated Circuit (ASIC), called PSEC6, in the TSMC 65nm process. It features 8 channels, a maximum sampling rate of 40 GSa/s, a buffer length of 204.8 nanoseconds, and a 10.24 GHz Phase Locked Loop (PLL), which is the first of its kind in the 65nm CMOS process. The event readout rate is 32 kHz, with the digitization done by an off-chip Analog-to-Digital Converter (ADC). Simulations predict a 4.0 GHz analog input bandwidth and 20 mW per channel during sampling; the 10.24 GHz PLL has a predicted jitter of 550 fs RMS at 15.7 mW. The paper describes the sampling architecture, chip signal paths, PLL design, and presents simulation results.
