Performance of a Front End prototype ASIC for picosecond precision time measurements with LGAD sensors
C. Agapopoulou, S. Blin, A. Blot, L. Castillo Garcia, M. Chmeissani, S. Conforti di Lorenzo, C. de La Taille, P. Dinaucourt, A. Fallou, J. Garcia Rodriguez, V. … 展开作者
C. Agapopoulou, S. Blin, A. Blot, L. Castillo Garcia, M. Chmeissani, S. Conforti di Lorenzo, C. de La Taille, P. Dinaucourt, A. Fallou, J. Garcia Rodriguez, V. Gkougkousis, C. Grieco, S. Grinstein, S. Guindon, N. Makovec, G. Martin-Chassard, G. Pellegrini, A. Rummler, S. Sacerdoti, N. Seguin Moreau, L. Serin, A. Tricoli
For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an excellent timing resolution below 50 ps. The front-end read-out ASIC must maintain the performance of the sensor, while keeping low power consumption. This paper presents the results on the first prototype of a front-end ASIC, named ALTIROC0, which contains the analog stages (preamplifier and discriminator) of the read-out chip. The ASIC was characterised both alone and as part of a module with a 2$\times$2 LGAD array of 1.1$\times$1.1 mm$^2$ pads bump-bonded to it. The various contributions of the electronics to the time resolution were investigated in test-bench measurements with a calibration setup. Both when the ASIC is alone or with a bump-bonded sensor, the jitter of the ASIC is better than 20 ps for an injected charge of 10 fC. The time walk effect that arises from the different response of the preamplifier for various injected charges can be corrected up to 10 ps using a Time Over Threshold measurement. The combined performance of the ASIC and the LGAD sensor, which was measured during a beam test campaign in October 2018 with pions of 120 GeV energy at the CERN SPS, is around 40 ps for all measured modules. All tested modules show good efficiency and time resolution uniformity.
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with \b{eta}-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplifi…
Temperature Dependence of Gain and Time Resolution in LGAD Detectors
Institute of High Energy Physics, Chinese Academy of Sciences（中国科学院高能物理研究所）；University of Chinese Academy of Sciences（中国科学院大学）；Spallation Neutron Source Science Center（散裂中子源科学中心）
This paper presents results that take a critical step toward proving 10 ps timing resolution's feasibility for particle identification in the TOPSiDE detector concept for the Electron-Ion Collider. Measurements of LGADs with a thickness of 35 micro-m and 50 micro-m are evaluated with a 120 GeV proton beam. The performance of the gain and timing response is assessed, including the dependence on the reverse bias voltage and operating temperature. The best timing resolution of UFSDs in a test beam to date is achieved using three combined planes of 35 micro-m thick LGADs at -30 degree celsius with…
The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate the performance of the analog frontend, with the goal to achieve 40 to 50 ps time resolution per hit with LGAD (therefore reach about 30ps per track with two detector-layer hits per track). ETROC0 consists of preamplifier and discriminator stages, which amplifies the LGAD signal and generates digital …
The development of detectors that provide high resolution in four dimensions has attracted wide-spread interest in the scientific community for applications in high-energy physics, nuclear physics, medical imaging, mass spectroscopy as well as quantum information. However, finding a technology capable of fulfilling such aspiration proved to be an arduous task. Among other silicon-based candidates, the Low-Gain Avalanche Diode (LGAD) has already shown excellent timing performances but proved to be unsuitable for fine pixelization. Therefore, the AC-coupled LGAD (AC-LGAD) approach was introduced…
We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16x16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most proba…
Silicon pad sensors with novel functions of higher timing resolution (LGAD: Low Gain Avalanche Detector) and higher position resolution (PSD: Position Sensitive Detector) are studied for an application to Silicon-Tungsten electromagnetic calorimeter for a detector of the International Linear Collider (ILC). Prototype sensors are fabricated, equipped with dedicated ASICs (Application-Specific Integrated Circuits) and tested with a positron beam as well as a radioisotope. The first results of the measurements of timing resolution with LGADs and position reconstruction with PSDs are reported.
In this paper we present a complete characterization of the first batch of Resistive AC-Coupled Silicon Detectors, called RSD1, designed at INFN Torino and manufactured by Fondazione Bruno Kessler (FBK) in Trento. With their 100% fill-factor, RSD represent the new enabling technology for high-precision 4D-tracking. Indeed, being based on the well-known charge multiplication mechanism of Low-Gain Avalanche Detectors (LGAD), they benefit from the very good timing performances of such technology together with an unprecedented resolution of the spatial tracking, which allows to reach the micron-le…
Switched capacitor arrays (SCA) ASICs are becoming more and more popular for the readout of detector signals, since the sampling frequency of typically several gigasamples per second allows excellent pile-up rejection and time measurements. They suffer however from the fact that their sampling bins are not equidistant in time, given by limitations of the chip process. In the past, this limited time measurements of optimal signals to standard deviations (σ) of about 4-25 ps in accuracy for the split pulse test, depending on the specific chip. This paper introduces a novel time calibration, whic…
Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS process for timing measurements, integrating a fully-depleted pixel matrix with a low-power BJT-based front-end per channel, integrated on the same 100 $μ m$ thick die. The target timing resolution is 30 ps RMS for electrons from the conversion of 511 keV photons. A novel synchronization scheme u…
We present a readout chip prototype for future pixel detectors with timing capabilities. The prototype is intended for characterizing 4D pixel arrays with a pixel size of $100\times100~μ\text{m}^2$, where the sensors are Low Gain Avalanche Diodes (LGADs). The long-term focus is towards a possible replacement of disks in the extended forward pixel system (TEPX) of the CMS experiment during the High Luminosity LHC (HL-LHC). The requirements for this ASIC are the incorporation of a Time to Digital Converter (TDC) within each pixel, low power consumption, and radiation tolerance up to $5\times10^{…
The basic principle of operation of silicon sensors with resistive read-out is built-in charge sharing. Resistive Silicon Detectors (RSD, also known as AC-LGAD), exploiting the signals seen on the electrodes surrounding the impact point, achieve excellent space and time resolutions even with very large pixels. In this paper, a TCT system using a 1064 nm picosecond laser is used to characterize sensors from the second RSD production at the Fondazione Bruno Kessler. The paper first introduces the parametrization of the errors in the determination of the position and time coordinates in RSD, then…
We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be a part of the readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for the CMS Endcap Timing Layer (ETL) of High-Luminosity LHC upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 W for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the Time of Arrival (TOA) and the Time over Threshold (TOT) measurements without delay control. A double-strobe self-calibratio…
