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arXiv 2407.01201hep-exphysics.ins-det
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配备新型快速读出 ASIC 的小直径 μ 子漂移管室在高本底计数率下的性能

Performance of small-diameter muon drift tube chambers with new fast readout ASIC at high background rates

Sergey Abovyan, Nayana Bangaru, Francesco Fallavollita, Oliver Kortner, Sandra Kortner, Hubert Kroha, Elena Voevodina, Robert Richter, Yazhou Zhao

备注：
Contribution to the 16th Pisa Meeting ( May 26, 2024 to June 1, 2024 La Biodola - Isola d'Elba (Italy)) submitted to publish in a special issue of Nuclear Instruments and Methods in Physics Research A
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AI总结：

面向未来高本底强子对撞机，本文研制 65 nm CMOS 快速前端芯片并结合 FPGA 自触发读出，测试表明 sMDT 在 1 MHz 下空间分辨率提升达 100 μm。

摘要：

HL-LHC 上的 ATLAS 等实验，或未来强子对撞机上的探测器，都需要在触发和离线重建两个层面都具备直至 TeV 量级优异动量分辨率的 μ 子探测器。这要求 μ 子径迹室即使在最高本底通量下也具有高空间分辨率。漂移管室是大面积 μ 子系统最具成本效益的技术，可提供所需的高计数率能力和三维空间分辨率。得益于电子学的进步，管径为 15 mm 的新一代小直径 μ 子漂移管（sMDT）探测器可在独立模式下使用，直至未来强子对撞机实验预期的本底计数率，无需额外的触发室即可提供事件时间和第二坐标。集成前端电子学的新进展包括成形信号的快速基线恢复，以及用于双面读出第二坐标测量的皮秒级时间数字转换器。现在，利用现代高性能 FPGA 进行实时模式识别和径迹重建，自触发运行已成为可能。为应对高本底通量，已研制出一款采用 65 nm TSMC CMOS 工艺、具有更高灵敏度和更快基线恢复能力的新型放大成形甄别器芯片。在 CERN 伽马辐照设施（GIF++），使用配备新型读出电子学的 sMDT 室开展了大量测试束活动。结果表明，在 1 MHz 本底计数率（即 100 TeV 对撞机实验预期的最高计数率）下，新芯片更短的峰值时间使漂移管的空间分辨率提高达 100 μm。

英文摘要：

Experiments like ATLAS at the HL-LHC or detectors at future hadron colliders need muon detectors with excellent momentum resolution up to the TeV scale both at the trigger and offline reconstruction levels. This requires muon tracking chambers with high spatial resolution even at the highest background fluxes. Drift-tube chambers are the most cost-effective technology for large-area muon systems, providing the required high rate capability and three-dimensional spatial resolution. Thanks to advances in electronics, the new generation small-diameter Muon Drift Tube (sMDT) detectors with 15 mm tube diameter can be used in stand-alone mode up to the background rates expected at future hadron collider experiments, providing event times and second coordinates without additional trigger chambers. New developments in integrated front-end electronics include fast baseline restoration of the shaped signal and picosecond time-to-digital converters for second coordinate measurement with double-sided read-out. Self-triggered operation is now possible using modern high-performance FPGAs for real-time pattern recognition and track reconstruction. A new amplifier shaper discriminator chip in 65 nm TSMC CMOS technology with increased sensitivity and faster baseline recovery has been developed to cope with high background fluxes. Extensive test beam campaigns using sMDT chambers with new readout electronics have been performed at the CERN Gamma Irradiation Facility (GIF++). Results show that the shorter peaking time of the new chip enhances the spatial resolution of the drift tubes by up to 100 $μ$m at a background rate of 1 MHz, the maximum rate expected at the 100 TeV collider experiment.

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