Verification is a critical aspect of designing front-end (FE) readout ASICs for High-Energy Physics (HEP) experiments. These ASICs share several similar functional features, resulting in similar verification objectives, which can be addressed using comparable verification strategies. This contribution presents a set of re-usable verification components for addressing common verification tasks, such as clock generation, reset handling, configuration, as well as hit and fault injections. The components were developed as part of the CHIPS initiative and they have been successfully used in the verification of multiple HEP ASICs.
High channel density and space restrictions required that the front end electronics integrated into the active elements of calorimeter. For that purpose novel readout chain base on Application-Specific Integrated Circuit (ASIC) designed for the Electromagnetic Calorimeter for the future International Linear Calorimeter experiment. In this paper, the performance study of ASIC with injected charge is presented.
One of candidates for the International Linear Collider(ILC)'s vertex detector is the Fine Pixel CCD (FPCCD) with a pixel size of 5 \times 5 (\mum^2). Sensor and readout systems are currently being studied and prototypes have been developed. In this paper we will report on the performance of latest developed readout ASIC prototype as well as the outline of the design strategy for the next ASIC prototype.
Multiple application-specific integrated circuits (ASIC) are required for the detectors if their readout channels are larger than that of ASIC channels. For a system with such a readout scheme, there is a need to configure channels among ASICs to achieve the lowest electronics noise and highest count rate. In this work, experiments were performed to investigate the performance of two different readout configurations between two ASICs in a cross-strip cadmium zinc telluride detector. A lower electronic noise level, better FWHM energy resolution performance, and higher count rate was found for t…
The next generation experiment in high energy particle physics will be International Linear Collider of electron and positron at the TeV scale. The experiment is aim to search the Higgs particle and to measure its properties. The physics program required the detector with high performance. One of the central detector is a Electromagnetic calorimeter, is going to measure the energy and position of high energy photons. Fine granularity and compactness brings to utilize the Si-W sampling detector. Due to high granularity the electromagnetic calorimeter will comprise of the order of $10^8$ readout…
We fabricated a readout ASIC with the fully depleted silicon-on-insulator (FD-SOI) technology for the pair-monitor. The pair-monitor is a silicon pixel device that measures the beam profile of the international linear collider. It utilizes the directional distribution of a large number of electron-positron pairs created by collision of bunches, and is required to tolerate radiation dose of about a few Mrad/year. The irradiation might cause the buried oxide layer of SOI to accumulate charges which interfere with intended functions. We thus performed extensive irradiation tests on the prototype …
The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 μm CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better …
A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors. The system mainly consists of three kinds of modules: the ASIC card, the Adapter card and the Front-End Card (FEC). The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The Adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the Adapter, has a FPGA-based reconfigurable logic and I/O interfaces, allowing users to choose various ASIC cards and Adapters for different types of det…
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also prese…
A detector emulator method has been developed. It allows for testing any readout electronics with realistic detector-like signals under controlled conditions, beyond the limits of any experiment based on radiation sources. It can substitute for expensive test-beam campaigns, or predict their results. The detector emulator is a powerful tool for the engineering of detector concepts, with its capability to reproduce any detector signal feature to test the electronics response. Here, the method is applied to the case of the VMM3a ASIC tested with sTGC detector emulated signals. Measurements of ch…
The water Cherenkov detector array (WCDA) is one of the key detectors in the large high altitude air shower observatory (LHAASO), which is proposed for very high gamma ray source survey. In WCDA, there are more than 3000 photomultiplier tubes (PMTs) scattered under water in an area of 80000 m2. As for the WCDA readout electronics, both high precision time and charge measurement is required over a large dynamic range from 1 photon electron (P.E.) to 4000 P.E. To reduce the electronics complexity and improve the system reliability, a readout scheme based on application specific integrated circui…
In the large-scale high energy physics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics. This flow was successfully implemented in the development of the readout ASIC prototypes for the muon chambers of the CBM experiment. Th…
A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel…
We present the design and the test results of a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld65 for detector front-end readout. LOCld65 is designed in a commercial 65-nm CMOS technology with a power supply of 1.2 V. LOCld65 contains two separate channels with the same structure and the two channels share an I2C slave. Each channel consists of an input amplifier, four stages of limiting amplifiers (LAs), a high-current output driver, and a bias-current generator. In order to extend the bandwidth, the input amplifier uses an inductive peaking technique and the LAs…
Calorimetry at future linear colliders could be based on a particle flow approach where granularity is the key to high jet energy resolution. Among different technologies, Micromegas chambers with 1 cm2 pad segmentation are studied for the active medium of a hadronic calorimeter. A chamber of 1 m2 with 9216 channels read out by a low noise front-end ASIC called MICROROC has recently been constructed and tested. Chamber design, ASIC circuitry and preliminary test beam results are reported.
The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC)…
We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 um CMOS technology (X-Fab XH035), consists of 64 readout channels, and has a function that performs simultaneous AD conversion for each channel. The equivalent noise charge of 54.9 e- +/- 11.3 e- (rms) is measured without connecting the ASIC to any detectors. From the spectroscopy measurements using a CdTe single-sided strip detector, the energy resolution of 1.12 keV (FWHM) is obtained at 13.9 keV, and photons withi…
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $μ$-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the S…
The main purpose of this work is to study the performance of the APV25 and VMM3a readout chips with regards to using them in the front-end readout system of a Triple-GEM detector. For the APV25, the Signal-to-Noise Ratio (SNR) was estimated with a cosmics measurement around 84.29 +/- 0.12. For the VMM3a, the noise of the chip was characterised in terms of the Equivalent Noise Charge (ENC) in the full parameter space and with increasing input capacitance. For the highest VMM gain and peaktime settings, the calculated ENC was about 300 electrons + 8 electrons/pF. Finally, a comparison was made b…
Particle physics detectors increasingly make use of custom FPGA firmware and application-specific integrated circuits (ASICs) for data readout and triggering. As these designs become more complex, it is important to ensure that they are simulated under realistic operating conditions before beginning fabrication. One tool to assist with the development of such designs is cocotb, an open source digital logic verification framework. Using cocotb, verification can be done at high level using the Python programming language, allowing sophisticated data flow simulations to be conducted and issues to…
Application Specific Integrated Circuits, ASICs, similar to those envisaged for the readout electronics of the central calorimeters of detectors for a future lepton collider have been exposed to high-energy electromagnetic showers. A salient feature of these calorimeters is that the readout electronics will be embedded into the calorimeter layers. In this article it is shown that interactions of shower particles in the volume of the readout electronics do not alter the noise pattern of the ASICs. No signal at or above the MIP level has been observed during the exposure. The upper limit at the …
High precision and large dynamic range measurement are required in the readout systems for the Water Cherenkov Detector Array (WCDA) in Large High Altitude Air Shower Observatory (LHAASO). This paper presents a prototype of 12-bit 40 MSPS Analog-to-Digital Converter (ADC) Application Specific Integrated Circuit (ASIC) designed for the readout of LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on power-efficient Successive Approximatio…
Low-Noise SiPM Light Readout and ASIC-Based Charge Readout of a Liquid Argon Time Projection Chamber for MeV Gamma-Ray Measurements
RIKEN Nishina Center（理化学研究所西崎中心）；University of Osaka（大阪大学）；Kavli IPMU, University of Tokyo（东京大学伽利略国际基础科学研究所）；University of Tokyo（东京大学）；Waseda University（早稻田大学）；Northeastern University（东北大学）
SKIROC2 is an ASIC to readout the silicon pad detectors for the electromagnetic calorimeter in the International Linear Collider. Characteristics of SKIROC2 and the new version of SKIROC2A, packaged with BGA, are measured with testboards and charge injection. The results on the signal-to-noise ratio of both trigger and ADC output, threshold tuning capability and timing resolution are presented.
The broad energy response, low electronic read noise, and good energy resolution have made X-ray Charge-Coupled Devices (CCDs) an obvious choice for developing soft X-ray astronomical instruments over the last half century. They also come in large array formats with small pixel sizes which make them a potential candidate for the next generation astronomical X-ray missions. However, the next generation X-ray telescopic experiments propose for significantly larger collecting area compared to the existing observatories in order to explore the low luminosity and high redshift X-ray universe which …
