This work presents the first measurements performed on the Timespot1 ASIC. As the second prototype developed for the TimeSPOT project, the ASIC features a 32x32 channels hybrid-pixel matrix. Targeted to space-time tracking applications in High Energy Physics experiments, the system aims to achieve a time resolution of 30 ps or better at a maximum event rate of 3 MHz per channel with a Data Driven interface. Power consumption can be programmed to range between $1.2W/cm^{2}$ and $2.6W/cm^{2}$. The presented results include a description of the ASIC operation and a first characterization of its performance in terms of time resolution.
We present the design and the performance of MUX64, a 64-to-1 analogue multiplexer ASIC for the ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one of its 64 inputs selected by six address lines for the voltages or temperatures being monitored to an lpGBT ADC channel. The prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared in wire-bonding and QFN88 packaging format. A total of 280 chips was examined for functionality and quality assurance. The accelerated aging test conducted at 85 degrees celsius shows negligible degradation over 16 days.
The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 μm CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better …
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also prese…
We report on the development of a front-end ASIC for silicon-strip detectors of the J-PARC Muon g-2/EDM experiment. This experiment aims to measure the muon anomalous magnetic moment and electric dipole moment precisely to explore new physics beyond the Standard Model. Since the time and momentum of positrons from muon decay are key information in the experiment, a fast response with high granularity is demanded to silicon-strip detectors as the positron tracker. The readout ASIC is thus required to tolerate a high hit rate of 1.4 MHz per strip and to have deep memory for the period of 40 us w…
The water Cherenkov detector array (WCDA) is one of the key detectors in the large high altitude air shower observatory (LHAASO), which is proposed for very high gamma ray source survey. In WCDA, there are more than 3000 photomultiplier tubes (PMTs) scattered under water in an area of 80000 m2. As for the WCDA readout electronics, both high precision time and charge measurement is required over a large dynamic range from 1 photon electron (P.E.) to 4000 P.E. To reduce the electronics complexity and improve the system reliability, a readout scheme based on application specific integrated circui…
For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an excellent timing resolution below 50 ps. The front-end read-out ASIC must maintain the performance of the sensor, while keeping low power consumption. This paper presents the results on the first prototype of a front-end ASIC, named ALTIROC0, which contains the analog stages (preamplifier an…
The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 μm CMOS prototype device contains two channels and each channel employs a SCA of 128 samples deep, a 12-bit Wilkinson ADC and a serial data readout. A series of tests have been conducted and the results indicate that: a full 1 V signal voltage range is available, the input analog bandwidth is approximately 450 MHz and the sampling speed is adjustable from 0.076 to 3.2 Gsps (Gigabit Samples Per Second). For precision waveform timing ext…
High channel density and space restrictions required that the front end electronics integrated into the active elements of calorimeter. For that purpose novel readout chain base on Application-Specific Integrated Circuit (ASIC) designed for the Electromagnetic Calorimeter for the future International Linear Calorimeter experiment. In this paper, the performance study of ASIC with injected charge is presented.
Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production
Carleton University（卡尔顿大学）；CERN（欧洲核子研究组织）；Rutherford Appleton Laboratories（卢瑟福阿普尔顿实验室）；University of Oxford（牛津大学）；University of Pennsylvania（宾夕法尼亚大学）；University College London（伦敦大学学院）；University of Victoria（维多利亚大学）
In this paper, we present the design and test results of LOCx2-130, a low-power, low-latency, dual-channel transmitter ASIC for detector front-end readout. LOCx2-130 has two channels of encoders and serializers, and each channel operates at 4.8 Gbps. LOCx2-130 can interface with three types of ADCs, an ASIC ADC and two COTS ADCs. LOCx2-130 is fabricated in a commercial 130-nm CMOS technology and is packaged in a 100-pin QFN package. LOCx2-130 consumes 440 mW and achieves a latency of less than 40.7 ns.
We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing performance evaluation, and includes all features necessary for the various operation modes, as well as the migration to the TSMC 130 nm CMOS technology. We present the TDC design with the emphasis on added features and performance optimization. Tests of the timing performance demonstrate that this ASIC meets the design specifications. The TDC has a bin size…
We developed a new front-end application specific integrated circuit (ASIC) for the upgrade of the Maia x-ray microprobe. The ASIC instruments 32 configurable front-end channels that perform either positive or negative charge amplification, pulse shaping, peak amplitude and time extraction along with buffered analog storage. At a gain of 3.6 V/fC, 1 $μ$s peaking time and a temperature of 248 K, an electronic resolution of 13- and 10 electrons rms was measured with and without a SDD sensor respectively. A spectral resolution of 170 eV FWHM at 5.9 keV was obtained with an $^{55}$Fe source. The c…
A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel…
We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 um CMOS technology (X-Fab XH035), consists of 64 readout channels, and has a function that performs simultaneous AD conversion for each channel. The equivalent noise charge of 54.9 e- +/- 11.3 e- (rms) is measured without connecting the ASIC to any detectors. From the spectroscopy measurements using a CdTe single-sided strip detector, the energy resolution of 1.12 keV (FWHM) is obtained at 13.9 keV, and photons withi…
We present the design and the test results of a dual-channel Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC LOCld65 for detector front-end readout. LOCld65 is designed in a commercial 65-nm CMOS technology with a power supply of 1.2 V. LOCld65 contains two separate channels with the same structure and the two channels share an I2C slave. Each channel consists of an input amplifier, four stages of limiting amplifiers (LAs), a high-current output driver, and a bias-current generator. In order to extend the bandwidth, the input amplifier uses an inductive peaking technique and the LAs…
The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC)…
In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25-um Silicon-on-Sapphire CMOS process and each channel operates at 5.12 Gbps, while LOCx2-130 is fabricated in a 130-nm bulk CMOS process and each channel operates at 4.8 Gbps. The power consumption and the transmission latency are 900 mW and 27 ns for LOCx2 and the corresponding simulation result of LOCx2-130 are 386 mW and 38 ns, respectively.
A 64-channel mixed-mode ASIC, suitable for particle detectors of large dynamic range and high capacitance up to hundreds of pF, is presented here. Each channel features an analogue front-end for signal amplification and filtering, and a mixed signal back-end to digitise and store the signal information. The analogue part consists of a low input-impedance programmable gain pre-amplifier based on a regulated common-gate (RCG) input stage, two shapers optimised for time and energy measurements. The back-end part mainly includes discriminators, TDCs and ADCs, which are used to process the signal a…
The upgrade of the ATLAS muon spectrometer for high-luminosity LHC requires new trigger and readout electronics for the various elements of the detector. We present the design of a time-to-digital converter (TDC) ASIC prototype for the ATLAS Monitored Drift Tube (MDT) detector. The chip was fabricated in a GlobalFoundries 130 nm CMOS technology. Studies indicate that its timing and power consumption characteristics meet the design specifications, with a timing bin variation of 40 ps for all 48 channels with a power consumption of about 6.5 mW per channel.
Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge informatio…
The timing performance of silicon sensors bump-bonded to Timepix3 ASICs is investigated, prior to and after different types of irradiation up to $8 \times 10^{15} 1 \mathrm{\,Me\kern -0.1em V} \mathrm{ \,n_{eq}} {\mathrm{ \,cm}}^{-2}$. The sensors have been tested with a beam of charged particles in two different configurations, perpendicular to and almost parallel to the incident beam. The second approach, known as the grazing angles method, is shown to be a powerful method to investigate not only the charge collection, but also the time-to-threshold properties as a function of the depth at w…
Application Specific Integrated Circuits, ASICs, similar to those envisaged for the readout electronics of the central calorimeters of detectors for a future lepton collider have been exposed to high-energy electromagnetic showers. A salient feature of these calorimeters is that the readout electronics will be embedded into the calorimeter layers. In this article it is shown that interactions of shower particles in the volume of the readout electronics do not alter the noise pattern of the ASICs. No signal at or above the MIP level has been observed during the exposure. The upper limit at the …
Quality control and quality assurance evaluation of ALFE2, a large-dynamic-range front-end ASIC de-veloped for the ATLAS Liquid Argon Calorimeter high-luminosity LHC upgrade
Physics Department, Brookhaven National Laboratory（布鲁克海文国家实验室物理系）；Instrumentation Department, Brookhaven National Laboratory（布鲁克海文国家实验室仪器部）；Department of Physics and Astronomy, Stony Brook University（石溪大学物理与天文系）；IJCLab, Université Paris-Saclay, CNRS/IN2P3（巴黎萨克雷大学IJCLab，CNRS/IN2P3）；ESAT-ADVISE, KU Leuven（荷语鲁汶大学ESAT-ADVISE）；CERN（欧洲核子研究中心）
A novel time calibration method for waveform sampling application specific integrated circuits (ASICs) based on switched capacitor arrays (SCAs) is proposed in this paper. Precision timing extraction using SCA ASICs has been proved to be a promising technique in many high energy physics experiments. However, such ASICs suffer from irregular sampling intervals caused by process variations. Therefore, careful calibration is required to improve the time resolution of such systems. We evaluated the limitation of a popular method using the proportionality between voltage amplitude and sampling inte…
The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions…
We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion $μ$-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the S…
Compact multi-channel radiation detectors rely on low noise front-end application specific integrated circuits (ASICs) to achieve high spectral resolution. Here, a new ASIC developed to readout virtual Frisch-grid cadmium zinc telluride (VFG CZT) detectors for gamma ray spectroscopy is presented. Corresponding to each ionizing event in the detector, the ASIC measures the amplitude and timing at the anode, the cathode and four pad sense electrodes associated with each sensor in a detector array. The ASIC is comprised of 52 channels of which there are 4 cathode channels and 48 channels which can…
Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray study with a primary scientific goal of indirect search of dark matter particles. As a crucial sub-detector, BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of…
We present the design and characterization of TIGER (Turin Integrated Gem Electronics for Readout), a 64-channel ASIC developed for the readout of the CGEM (Cylindrical Gas Electron Multiplier) detector, the proposed inner tracker for the 2018 upgrade of the BESIII experiment, carried out at BEPCII in Beijing. Each ASIC channel features a charge sensitive amplifier coupled to a dual-branch shaper stage, optimized for timing and charge measurement, followed by a mixed-mode back-end that extracts and digitizes the timestamp and charge of the input signals. The time-of-arrival is provided by a se…
The Large High Altitude Air Shower Observatory is in the R&D phase, in which the Water Cherenkov Detector Array is an important part. The signals of Photo-Multiplier Tubes would vary from single photo electron to 4000 photo electrons, and both high precision charge and time measurement is required. To simplify the signal processing chain, the charge-to-time conversion method is employed. A prototype of the front-end readout ASIC is designed and fabricated in Chartered 0.35 μm CMOS technology, which integrates time disctrimination and converts the input charge information to pulse widths. With …
The impressive progress in data rate capabilities, pattern recognition, and spatial resolution of current detectors in experimental particle physics has been possible thanks to the availability of sophisticated analog processors combined with complex digital signal processors implemented in custom made front end ASICs. The demands in terms of performance and increasingly smaller feature sizes are significant. In order to meet these instrumentation challenges, we need to educate and retain a skilled work force, as well as aggregate design tools and acquired knowledge. We propose a multifaceted …
This paper presents a small-area monolithic pixel detector ASIC designed in 130 nm SiGe BiCMOS technology for the upgrade of the pre-shower detector of the FASER experiment at CERN. The purpose of this prototype is to study the integration of fast front-end electronics inside the sensitive area of the pixels and to identify the configuration that could satisfy at best the specifications of the experiment. Self-induced noise, instabilities and cross-talk were minimised to cope with the several challenges associated to the integration of pre-amplifiers and discriminators inside the pixels. The m…
Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS process for timing measurements, integrating a fully-depleted pixel matrix with a low-power BJT-based front-end per channel, integrated on the same 100 $μ m$ thick die. The target timing resolution is 30 ps RMS for electrons from the conversion of 511 keV photons. A novel synchronization scheme u…
This writeup summarizes the work of the Topical Working Group 7 of the Instrumentation Frontier group of the Snowmass 2021 process. Group 'IF07' dealt with issues pertaining to ASICs and Readout Electronics. The community efforts as part of IF07 were organized across 7 white papers submitted to the Snowmass process and available in the arXiv.
This work reports a cost-effective, simple front-end readout and DAQ of a RPC-based muon scattering tomography system under construction. The Time-over-threshold property of NINO ASICs has been exploited to achieve precise tracking by extraction of position information. The use of a low-cost FPGA for event selection and TOT measurement has been demonstrated for a prototype RPC which has been triggered by a cosmic ray hodoscope of three plastic scintillators. The relation between input pulse width and TOT has been established by analyzing the waveforms of the RPC signals. The TOT profile at dif…
Development and characterization of hybrid MCP-PMT with embedded Timepix4 ASIC used as pixelated anode
INFN, Division of Ferrara（意大利国家核物理研究所费拉拉分部）；Dept. of Physics and Earth Science, University of Ferrara（费拉拉大学地球科学与物理学系）；EP Department, CERN（欧洲核子研究中心实验物理部）
We report on the design and testing of novel mixed analog and digital front end ASICs custom made for the single photon detectors considered for the BTeV RICH system. The key features are reviewed, as well as results achieved using electronics bench tests and beam studies.
A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's…
A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors. The system mainly consists of three kinds of modules: the ASIC card, the Adapter card and the Front-End Card (FEC). The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The Adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the Adapter, has a FPGA-based reconfigurable logic and I/O interfaces, allowing users to choose various ASIC cards and Adapters for different types of det…
Application Specific Integrated Circuits (ASICs) are used in space-borne instruments for signal processing and detector readout. The electrical interface of these ASICs to frontend printed circuit boards (PCBs) is commonly accomplished with wire bonds. Through Silicon Via (TSV) technology has been proposed as an alternative interconnect technique that will reduce assembly complexity of ASIC packaging by replacing wire bonding with flip-chip bonding. TSV technology is advantageous in large detector arrays where TSVs enable close detector tiling on all sides. Wafer-level probe card testing of TS…
Fermi National Accelerator Laboratory（费米国家加速器实验室）；Northwestern University（西北大学）；Columbia University（哥伦比亚大学）；UC San Diego（加州大学圣迭戈分校）；Massachusetts Institute of Technology（麻省理工学院）；Brown University（布朗大学）；California Institute of Technology（加州理工学院）；Florida Institute of Technology（佛罗里达理工学院）
Despite advances in the programmable logic capabilities of modern trigger systems, a significant bottleneck remains in the amount of data to be transported from the detector to off-detector logic where trigger decisions are made. We demonstrate that a neural network autoencoder model can be implemented in a radiation tolerant ASIC to perform lossy data compression alleviating the data transmission problem while preserving critical information of the detector energy profile. For our application, we consider the high-granularity calorimeter from the CMS experiment at the CERN Large Hadron Collid…
We report on the recent development of a versatile analog front-end compatible with a negative-ion $μ$-TPC for a directional dark matter search as well as a dual-phase, next-generation $\mathcal{O}$(10~kt) liquid argon TPC to study neutrino oscillations, nucleon decay, and astrophysical neutrinos. Although the operating conditions for negative-ion and liquid argon TPCs are quite different (room temperature \textit{vs.} $\sim$88~K operation, respectively), the readout electronics requirements are similar. Both require a wide-dynamic range up to 1600 fC, and less than 2000--5000 e$^-$ noise for …
A dedicated front-end electronics has been developed for the trigger chambers of the ALICE muon spectrometer which will work at the future LHC at CERN. These trigger chambers are based on RPCs (Resistive Plate Chambers) working in streamer mode. The number of electronics channels (about 21000) and the fact that RPC pulsed signals have specific characteristics have led to design a 8 channels front-end ASIC using a new discrimination technique. The principle of the ASIC is described and the radiation hardness is discussed. Special emphasis is put on production characteristics of about 4000 chips…
Operating HADES at the future FAIR SIS-100 accelerator challenges the rate capability of DAQ and electronics. A new, more robust version of front-end electronics needs to be built for the HADES drift chamber system. Due to the unavailability of the previously used ASD-8 analog read-out ASIC, PASTTREC (PANDA straw tube read-out ASIC) was tested as an ASD-8 replacement in different scenarios including a beam test. PASTTREC falls 20% short of the ASD-8 time precision but performs better w.r.t. signal charge measurements and overall operation stability. The measured time precision as a function of…
We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with \b{eta}-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplifi…
The FERS-5200 is the new CAEN Front-End Readout System for large detector arrays. It consists in a compact, distributed and easy-deployable solution integrating front-end based on ASICs, A/D conversion, data processing, synchronization and readout. Using the appropriate Front-End the solution perfectly fits a wide range of detectors such as SiPMs, multianode PMTs, GEMs, Silicon Strip detectors, Wire Chambers, Gas Tubes, etc. The first member of the FERS family is the unit A5202, a 64 channel readout card for SiPMs, based on the CITIROC ASIC by Weeroc SaS. The Concentrator board DT5215 can mana…
