The same charge sensitive preamplifier and discriminator circuit with different isolation strategies has been tested to compare the isolation of both analog and digital circuits from the substrate of a 65nm bulk CMOS process to the isolation of only digital circuits, tying analog ground locally to the substrate. This study will show that the circuit with analog on the substrate and digital in deep N-well has better noise isolation between analog and digital.
In the context of the Silicon tracking for a Linear Collider (SiLC) R&D collaboration, a highly compact mixed-signal chip has been designed in 130nm CMOS technology intended to read Silicon strip detectors for the experiments at the future International Linear Collider. The chip includes eighty eight channels of a full analog signal processing chain and analog to digital conversion with the corresponding digital controls and readout channels. The chip is 5x10mm2 where the analog implementation represents 4/5 of the total Silicon area.
We describe the new fast timing readout chip SAMPIC developed in CEA Saclay and in LAL Orsay (France) as well as the results of differents tests performed using that chip.
Hybrid silicon pixel detectors are currently used in the innermost tracking system of the Compact Muon Solenoid (CMS) experiment. Radiation tolerance up to fluences expected for a few years of running of the Large Hadron Collider (LHC) has already been proved, although some degradation of the part of the silicon detector closer to the interaction point is expected. During the LHC upgrade phases, the level of dose foreseen for the silicon pixel detector will be much higher. To face this aspect, dedicated irradiation tests with fluences above $\mathcal{O}(10^{15})$ n$_{\textrm{eq}}$/cm$^2$ have …
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (…
The current CMS silicon pixel detector as the innermost component of the CMS experiment is performing well at LHC design luminosity, but would be subject to severe inefficiencies at LHC peak luminosities of 2x10e34 cm^-2 s^-1. Therefore, an upgrade of the CMS pixel detector is planned, including a new readout chip. The chip design comprises additional on-chip buffer cells as well as high-speed data links and low-threshold comparators in the pixel cells. With these changes the upgraded pixel detector will be able to maintain or even improve the efficiency of the current detector at the increase…
With the ultimate goal of developing a pixel-based readout for a TPC at the ILC, a GridPix readout system consisting of one Timepix3 chip with an integrated amplification grid was embedded in a prototype detector. The performance was studied in a testbeam with 2.5 GeV electrons at the ELSA accelerator in Bonn. The error on the track position measurement both in the drift direction and in the readout plane is dominated by diffusion. Systematic uncertainties are limited to below 10 $μ$m. The GridPix can detect single ionization electrons with high efficiency, which allows for energy loss measure…
The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4…
The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environm…
The readout chip for the CMS pixel detector has to deal with an enormous data rate. On-chip zero suppression is inevitable and hit data must be buffered locally during the latency of the first level trigger. Dead-time must be kept at a minimum. It is dominated by contributions coming from the readout. To keep it low an analog readout scheme has been adopted where pixel addresses are analog coded. We present the architecture of the final CMS pixel detector readout chip with special emphasis on the analog readout chain. Measurements of its performance are discussed.
Calorimetry at future linear colliders could be based on a particle flow approach where granularity is the key to high jet energy resolution. Among different technologies, Micromegas chambers with 1 cm2 pad segmentation are studied for the active medium of a hadronic calorimeter. A chamber of 1 m2 with 9216 channels read out by a low noise front-end ASIC called MICROROC has recently been constructed and tested. Chamber design, ASIC circuitry and preliminary test beam results are reported.
We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.
The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a de…
A new silicon-strip readout chip named "SliT" has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment at J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates a conventional charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators for each of 128 identical channels. A digital part includes storage memories, an event building block, a serializer, and LVDS drivers. A distinct feature of the SliT is utilization of the zero-cross architecture, w…
Mu3e is a novel experiment searching for charged lepton flavor violation in the rare decay $μ^+ \rightarrow e^+e^-e^+$. Decay vertex position, decay time and particle momenta have to be precisely measured in order to reject both accidental and physics background. A silicon pixel tracker based on $50\,μ$m thin high voltage monolithic active pixel sensors (HV-MAPS) in a 1 T solenoidal magnetic field provides precise vertex and momentum information. The MuPix chip combines pixel sensor cells with integrated analog electronics and a periphery with a complete digital readout. The MuPix7 is the firs…
The phase-2 upgrade of the LHC will require novel pixel readout chips, which deliver hit information at drastically increased data rates and tolerate unprecedented radiation levels. The large-scale prototype chip RD53A has been designed by the RD53 collaboration and manufactured in a 65 nm CMOS process, suitable for the innermost layers of both the ATLAS and the CMS experiment. In order to verify the radiation hardness design goal of 500 Mrad total ionizing dose, RD53A has been irradiated using X-rays. The radiation effects on the performance of the data link, reset circuit and the clock gener…
We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discrimi…
The CMS collaboration is building a new inner tracking pixel detector for the High-Luminosity LHC. Each pixel readout chip will be controlled with a single serial input stream at 160 Mbps and will send out data via four current mode logic (CML) 1.28 Gbps outputs. The readout chips will be grouped in modules and connected with up to 1.6 meters long low-mass electrical links to Low-Power Gigabit Transceivers (lpGBT) and Versatile Link PLUS Transceiver (VTRx+) modules that send the data optically to off-detector electronics at 10 Gbps. The characterization of these components and system tests of …
In September 2008 the Slim5 collaboration submitted a low material budget silicon demonstrator to test with 12 GeV/c protons, at the PS-T9 test-beam at CERN. Inside the reference telescope, two different detectors were placed as device under test (DUT). The first was a 4k-Pixel Matrix of Deep N Well MAPS, developed in a 130 nm CMOS Technology, providing digital sparsified readout. The other one was a high resistivity double sided silicon detector, with short strips at 45-degree angle to the detector's edge, read out by the FSSR2 chip. The FSSR2 is a 128 channel data-driven fast readout chip de…
Small-diameter Drift Tube (sMDT) detectors with 15 mm tube diameter have proven to be excellent candidates for precision muon tracking detectors in experiments at future hadron colliders like HL-LHC and FCC-hh where unprecedentedly high background rate capabilities are required. sMDT chambers are currently being installed in the inner barrel layer of the ATLAS muon spectrometer. The rate capability of the sMDT drift tubes in terms of muon detection efficiency and spatial resolution is limited by the performance of the readout electronics. A new (s)MDT ASD (Amplifier-Shaper-Discriminator) reado…
The CMS pixel detector consists of approximately 66 million silicon pixels whose analog signals are read out by 15,840 programmable Readout Chips. With the recent startup of the LHC, the detector is now collecting data used for precise vertexing and track-finding. In preparation for data taking, the detector's Readout Chips and their supporting readout and control electronics were calibrated. The calibration that has taken place since the detector's installation in the summer of 2008 will be described. These calibrations focused on the optimization of the Readout Chips' thresholds and analog r…
The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three…
We have operated a Medipix2 CMOS readout chip, with amplifying, shaping and charge discriminating front-end electronics integrated on the pixel-level, as a highly segmented direct charge collecting anode in a three-stage gas electron multiplier (Triple-GEM) to detect the ionization from $^{55}$Fe X-rays and electrons from $^{106}$Ru. The device allows to perform moderate energy spectroscopy measurements (20 % FWHM at 5.9 keV $X$-rays) using only digital readout and two discriminator thresholds. Being a truly 2D-detector, it allows to observe individual clusters of minimum ionizing charged part…
Various chips for the silicon sensors measurements are described. These chips are based on 0.35 um and 0.18um CMOS technology. Several analog chips together with self-trigger /derandomizer one allow to measure silicon sensors designed for different purposes. Tracking systems, calorimeters, particle charge measurement system and other application sensors can be investigated by the integrated circuit readout with laser or radioactive sources. Also electrical parameters of silicon sensors can be studied by such test setup.
High-rate, high-resolution single photon X-ray imaging: Medipix4, a large 4-side buttable pixel readout chip with high granularity and spectroscopic capabilities
This paper describes an iterative method of per-pixel energy calibration of hybrid pixel detectors with GaAs:Cr sensor and Timepix readout chip. A convolution of precisely measured spectra of characteristic X-rays of different metals with the resolution and the efficiency of the pixel detector is used for the calibration. The energy resolution of the detector is also measured during the calibration. The use of per-pixel calibration allows to achieve a good energy resolution of the Timepix detector with GaAs:Cr sensor: 8% and 13% at 60 keV and 20 keV, respectively.
The RD50-CMOS group aims to design and study High Voltage CMOS (HVCMOS) chips for use in a high radiation environment. Currently, measurements are performed on RD50-MPW2 chip, the second prototype developed by this group. The active matrix of the prototype consists of 8x8 pixels with analog front end. Details of the analog front end and simulations have been already published earlier. This contribution focuses on the Caribou based readout system of the active matrix. Each pixel of the active matrix can be readout one after the other. Relevant aspects of hardware, firmware and software are intr…
A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel…
Results obtained with 3D columnar pixel sensors bump-bonded to the RD53A prototype readout chip are reported. The interconnected modules have been tested in a hadron beam before and after irradiation to a fluence of about $1\times$$10^{16}$neq cm$^{-2}$ (1MeV equivalent neutrons). All presented results are part of the CMS R&D activities in view of the pixel detector upgrade for the High Luminosity phase of the LHC at CERN (HL-LHC). A preliminary analysis of the collected data shows hit detection efficiencies around 97% measured after proton irradiation.
The average minimum number of bits needed for lossless readout of a pixel detector is calculated, in the regime of interest for particle physics where only a small fraction of pixels have a non-zero value per frame. This permits a systematic comparison of the readout efficiency of different encoding imple- mentations. The calculation is compared to the number of bits used by the FE-I4 pixel readout chip of the ATLAS experiment.
The Extended Analogue Silicon Photo-multiplier Integrated Read Out Chip, EASIROC, is a chip proposed as front-end of the camera at the focal plane of the imaging Cherenkov ASTRI SST-2M telescope prototype. This paper presents the results of the measurements performed to characterize EASIROC in order to evaluate its compliance with the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger time walk and the jitter effects as a function of the pulse amplitude. The EASIROC output signal is found to vary linearly as a function of the input pulse amplitude with very low l…
A small drift chamber was read out by means of a MediPix2 readout chip as direct anode. A Micromegas foil was placed 50 $μ$m above the chip, and electron multiplication occurred in the gap. With a He/Isobutane 80/20 mixture, gas multiplication factors up to tens of thousands were achieved, resulting in an efficiency for detecting single electrons of better than 90% . We recorded many frames containing 2D images with tracks from cosmic muons. Along these tracks, electron clusters were observed, as well as delta-rays.
A scalable readout system (SRS) is designed to provide a general solution for different micro-pattern gas detectors. The system mainly consists of three kinds of modules: the ASIC card, the Adapter card and the Front-End Card (FEC). The ASIC cards, mounted with particular ASIC chips, are designed for receiving detector signals. The Adapter card is in charge of digitizing the output signals from several ASIC cards. The FEC, edged-mounted with the Adapter, has a FPGA-based reconfigurable logic and I/O interfaces, allowing users to choose various ASIC cards and Adapters for different types of det…
PARISROC is a complete read out chip, in AMS SiGe 0.35 micron technology, for photomultipliers array. It is a front-end electronics ASIC which allows triggerless acquisition for the next generation of neutrino experiments. These detectors have place in megaton size water tanks and will require very large surface of photo-detection. An R & D program, funded by French national agency for research and called PMm2, proposes to segment the very large surface of photo-detection in macro pixels made of 16 photomultiplier tubes connected to an autonomous front-end electronics. The ASIC allows triggerl…
A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference
Instituto Balseiro（巴尔塞罗研究所）；Instituto de Nanociencia y Nanotecnología INN (CNEA-CONICET)（纳米科学与技术研究所（CNEA-CONICET））；Fermi National Accelerator Laboratory（费米国家加速器实验室）；Universidad Nacional de Córdoba（科尔多瓦国立大学）；Comisión Nacional de Energía Atómica (CNEA)（国家原子能委员会）；CONICET（阿根廷国家科学研究委员会）
PARISROC is a complete read out chip, in AMS SiGe 0.35 micron technology [1], for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for research (ANR) called PMm2: Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles [2] (ref.ANR-06-BLAN- 0186). The ASIC integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC and a 24-bit Counter. The charge measurement should…
The main purpose of this work is to study the performance of the APV25 and VMM3a readout chips with regards to using them in the front-end readout system of a Triple-GEM detector. For the APV25, the Signal-to-Noise Ratio (SNR) was estimated with a cosmics measurement around 84.29 +/- 0.12. For the VMM3a, the noise of the chip was characterised in terms of the Equivalent Noise Charge (ENC) in the full parameter space and with increasing input capacitance. For the highest VMM gain and peaktime settings, the calculated ENC was about 300 electrons + 8 electrons/pF. Finally, a comparison was made b…
The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3 x 10^34 cm^-2 s^-1 with an integrated luminosity over the IBL lifetime of 300 fb^-1 corresponding to a design lifetime fluence of 5 x 10^15 n_eq cm^-2 and ionizing dose of 250 Mrad including safety factors. The production f…
Traditional thermal neutron detectors are based on Helium-3 as conversion and detection material due to its large neutron cross-section. In light of the upgrade and construction of several neutron scattering facilities such as the European Spallation Source (ESS) and a simultaneous shortage of Helium-3, new detection technologies have been introduced. The most prominent one is to use solid converts with a large thermal neutron cross-section such as Gadolinium and Boron. Those materials emit charged particles when hit by a neutron. The technique then relies on detection and/or tracking of the c…
BDAQ53 is a readout system and verification framework for hybrid pixel detector readout chips of the RD53 family. These chips are designed for the upgrade of the inner tracking detectors of the ATLAS and CMS experiments. BDAQ53 is used in applications where versatility and rapid customization are required, such as in laboratory testing environments, test beam campaigns, and permanent setups for quality control measurements. It consists of custom and commercial hardware, a Python-based software framework, and FPGA firmware. BDAQ53 is developed as open source software with both software and firm…
We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16x16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most proba…
Depleted CMOS active sensors (DMAPS) are being developed for high-energy particle physics experiments in high radiation environments, such as in the ATLAS High Luminosity Large Hadron Collider (HL-LHC). Since charge collection by drift is mandatory for harsh radiation environment, the application of high bias voltage to high resistive sensor material is needed. In this work, a prototype of a DMAPS was fabricated in a 150nm CMOS process on a substrate with a resistivity of >2 kΩcm that was thinned to 100 μm. Full depletion occurs around 20V, which is far below the breakdown voltage of 110 V. A …
An eight chip InGrid module has been tested as readout of a prototype time projection chamber. The construction of the modules as well as first preliminary results are presented. The InGrids, a Micromegas like amplification structure with a pixel ASIC, have been produced on wafer-level in a photolithographic process. For the measurements a newly developed readout system based on the Scalable Readout System was used.
The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 μm CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better …
The development of detectors that provide high resolution in four dimensions has attracted wide-spread interest in the scientific community for applications in high-energy physics, nuclear physics, medical imaging, mass spectroscopy as well as quantum information. However, finding a technology capable of fulfilling such aspiration proved to be an arduous task. Among other silicon-based candidates, the Low-Gain Avalanche Diode (LGAD) has already shown excellent timing performances but proved to be unsuitable for fine pixelization. Therefore, the AC-coupled LGAD (AC-LGAD) approach was introduced…
We evaluate the performances of a 100 um-thick silicon strip detector (SSD) with a 300 MeV proton beam and a 90Sr beta-ray source. Signals from the SSD have been read out using a VLSI chip. Common-mode noise, signal separation efficiency and energy resolution are compared with those for the SSD's with a thickness of 300 um and 500 um. Energy resolution for minimum ionizing particles (MIP's) is improved by fitting the non-constant component in a common-mode noise with a linear function.
The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial $180$ nm HV-CMOS process and contains a matrix of $128\times128$ square pixels with $25$ $μ$m pitch. First prototypes have been produced with a standard resistivity of $\sim20$ $Ω$cm for the substrate and tested in standalone mode.…
We present the development of an automated testing system for the VMM hybrid of the RD51 collaboration. The VMM hybrid is a new front-end board for the RD51 common readout system, the Scalable Readout System, and will become the workhorse for the next decade to read out Micro-Pattern Gaseous Detectors. It uses the VMM chip developed for the ATLAS New Small Wheel to convert charge signals from detectors to digital data. Our testing system automatically characterises the quality of the VMM chips on the hybrid after production during multiple tests. Results are evaluated to classify the chips and…
