Readout system and testbeam results of the RD50-MPW2 HV-CMOS pixel chip
Patrick Sieberer, Thomas Bergauer, Klemens Floeckner, Christian Irmler, Helmut Steininger
备注：
Published under licence in Journal of Physics: Conference Series by IOP Publishing Ltd. CC-BY Content from this work may be used under the terms of the Creative Commons Attribution 4.0 International licence. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI
发表信息：
Journal of Physics: Conference Series. Volume 2374. 2022. 012096
The RD50-CMOS group aims to design and study High Voltage CMOS (HVCMOS) chips for use in a high radiation environment. Currently, measurements are performed on RD50-MPW2 chip, the second prototype developed by this group. The active matrix of the prototype consists of 8x8 pixels with analog front end. Details of the analog front end and simulations have been already published earlier. This contribution focuses on the Caribou based readout system of the active matrix. Each pixel of the active matrix can be readout one after the other. Relevant aspects of hardware, firmware and software are introduced. As a first stage, firmware for a standalone setup is introduced and details on data flow are given. Afterwards, a second stage of the firmware capable of synchronizing with other detectors and accepting triggers is presented, focusing on operation of the chip in combination with a tracking telescope to measure efficiency and residuals.
HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the $4^{\mathrm{th}}$ generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between $1\cdot 10^{14}$ and $5\cdot 10^{15}$ 1-MeV-n$_\textrm{eq}$/cm$^2$. T…
The ALICE Inner Tracking System has been recently upgraded to a full silicon detector consisting entirely of MAPS, arranged in seven concentric layers around the LHC beam pipe. Further ahead, during the LHC Long Shutdown 3, the ALICE collaboration is planning to replace the three innermost layers of this new ITS with a novel vertex detector. The proposed design features wafer-scale, ultra-thin, truly cylindrical MAPS. The new sensors will be thinned down to 20-40~{\textmu}m, featuring a material budget of less than 0.05\%~x/$\mathrm{X_{0}}$ per layer, unprecedented low, and will be arranged co…
The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$μ$m $\times$ 50$μ$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successi…
The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a de…
Depleted monolithic CMOS active pixel sensors (DMAPS) have been developed in order to demonstrate their suitability as pixel detectors in the outer layers of a toroidal LHC apparatus inner tracker (ATLAS ITk) pixel detector in the high-luminosity large hadron collider (HL-LHC). Two prototypes have been fabricated using 150 nm CMOS technology on high resistivity (> 2 k$Ω$ $cm^2$) wafers. The chip size is equivalent to that of the current ATLAS pixel detector readout chip. One of the prototypes is used for detailed characterization of the sensor and the analog readout of the DMAPS. The other is …
We present a readout scheme for CMOS image sensors that can be used to achieve arbitrarily high dynamic range (HDR) in principle. The linear full well capacity (LFWC) in high signal regions was extended 50 times from 20 ke$^{-}$ to 984 ke$^{-}$ via an interlaced row-wise readout order, whilst the noise floor remained unchanged in low signal regions, resulting in a 34 dB increase in DR. The peak signal-to-noise ratio (PSNR) is increased in a continuous fashion from 43 dB to 60 dB. This was achieved by summing user-selected rows which were read out multiple times. Centroiding uncertainties were …
Purpose Nanopore-based molecular sensing and measurement, specifically Deoxyribonucleic acid (DNA) sequencing, is advancing at a fast pace. Some embodiments have matured from coarse particle counters to enabling full human genome assembly. This evolution has been powered not only by improvements in the sensors themselves, but also in the assisting microelectronic Complementary Metal Oxide Semiconductor (CMOS) readout circuitry closely interfaced to them. In this light, this paper reviews established and emerging nanopore-based sensing modalities considered for DNA sequencing and CMOS microelec…
In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25-um Silicon-on-Sapphire CMOS process and each channel operates at 5.12 Gbps, while LOCx2-130 is fabricated in a 130-nm bulk CMOS process and each channel operates at 4.8 Gbps. The power consumption and the transmission latency are 900 mW and 27 ns for LOCx2 and the corresponding simulation result of LOCx2-130 are 386 mW and 38 ns, respectively.
The Mu3e experiment is searching for the charged lepton flavour violating decay $ μ^+\rightarrow e^+ e^- e^+ $, aiming for an ultimate sensitivity of one in $10^{16}$ decays. In an environment of up to $10^9$ muon decays per second the detector needs to provide precise vertex, time and momentum information to suppress accidental and physics background. The detector consists of cylindrical layers of $50\, μ\text{m}$ thin High Voltage Monolithic Active Pixel Sensors (HV-MAPS) placed in a $1\,\text{T}$ magnetic field. The measurement of the trajectories of the decay particles allows for a precise…
Pixel sensors based on commercial high-voltage CMOS processes are an exciting technology that is considered as an option for the outer layer of the ATLAS inner tracker upgrade at the High Luminosity LHC. Here, charged particles are detected using deep n-wells as sensor diodes with the depleted region extending into the silicon bulk. Both analog and digital readout electronics can be added to achieve different levels of integration up to a fully monolithic sensor. Small scale prototypes using the ams CMOS technology have previously demonstrated that it can achieve the required radiation toleran…
The present article introduces a novel ASIC architecture, designed in the context of the ATLAS Tile Calorimeter upgrade program for the High-Luminosity phase of the Large Hadron Collider at CERN. The architecture is based on radiation-tolerant 130 nm Complementary Metal-Oxide-Semiconductor technology, embedding both analog and digital processing of detector signals. A detailed description of the ASIC is given in terms of motivation, design characteristics and simulated and measured performance. Experimental studies, based on 24 prototype units under real particle beam conditions are also prese…
We present the design and the absolute calibration of charged particle high-repetition-rate online readout CMOS system tailored for high-power laser experiments. This system equips a Thomson parabola (TP) spectrometer, used at the Apollon petawatt scale laser facility to measure the spectra of protons produced by high-intensity laser-target interactions. The RadEye1 CMOS matrixes array detectors are paired with a custom triggering system for image grabbing. This allows us to register the proton and ion signals remotely at a high-repetition-rate. The latter is presently of one shot/min, but the…
This paper focuses on the conversion gain (CG) of pixels implementing pinned photo-diodes (PPD) and in-pixel voltage follower in standard CMOS image sensor (CIS) process. An overview of the CG expression and its impact on the noise performance of the CIS readout chain is presented. CG enhancement techniques involving process refinements and pure circuit design and pixel scheme optimization are introduced. The implementation of these techniques in a 180 nm CIS process demonstrates a progressive enhancement of the CG by more than a factor 3 with respect to a standard reference pixel from the sam…
We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm technology, featuring a $32 \times 32$ pixel matrix with a pitch of $55 ~ μm$. Timespot1 is the first small-size prototype, conceived to readout fine-pitch pixels with single-hit time resolution below $50 ~ ps_\text{rms}$ and input rates of several hundreds of kilohertz per pixel. Such experimental conditions will be typical of the next generation of high-luminosity collider experiments, from the LHC run5 and beyond. Each pixel of the ASIC includes a charge amplifier, a discriminator, and a Time-to-Digit…
In view of the tracking detector application to the ATLAS High Luminosity LHC (HL-LHC) upgrade, we have developed a new generation of High Voltage CMOS (HV-CMOS) monolithic pixel-sensor prototypes featuring the AMS aH18 (180 nm) commercial CMOS technology. By fully integrating both analog and digital readout-circuitry on the same particle-detecting substrate, current challenges of hybrid sensor technologies, i.e., larger readout input-capacitance, lower production-yield, and higher production and integration cost, can be downscaled. The large electrode design using high-resistivity substrates …
CMOS Image Sensors for CEvNS Detection at Nuclear Reactors
University of Chicago（芝加哥大学）；Universidad de Buenos Aires, Facultad de Ciencias Exactas y Naturales（布宜诺斯艾利斯大学理学院）；CONICET, Universidad de Buenos Aires, Instituto de Física de Buenos Aires (IFIBA)（阿根廷国家科学研究委员会，布宜诺斯艾利斯大学，布宜诺斯艾利斯物理研究所）；CONICET, Instituto de Física Enrique Gaviola (IFEG), Comisión Nacional de Energía Atómica (CNEA) and Universidad Nacional de Córdoba（阿根廷国家科学研究委员会，恩里克·加维奥拉物理研究所，国家原子能委员会和科尔多瓦国立大学）
The phase-2 upgrade of the LHC will require novel pixel readout chips, which deliver hit information at drastically increased data rates and tolerate unprecedented radiation levels. The large-scale prototype chip RD53A has been designed by the RD53 collaboration and manufactured in a 65 nm CMOS process, suitable for the innermost layers of both the ATLAS and the CMS experiment. In order to verify the radiation hardness design goal of 500 Mrad total ionizing dose, RD53A has been irradiated using X-rays. The radiation effects on the performance of the data link, reset circuit and the clock gener…
With the ultimate goal of developing a pixel-based readout for a TPC at the ILC, a GridPix readout system consisting of one Timepix3 chip with an integrated amplification grid was embedded in a prototype detector. The performance was studied in a testbeam with 2.5 GeV electrons at the ELSA accelerator in Bonn. The error on the track position measurement both in the drift direction and in the readout plane is dominated by diffusion. Systematic uncertainties are limited to below 10 $μ$m. The GridPix can detect single ionization electrons with high efficiency, which allows for energy loss measure…
The radiation hardness of passive CMOS pixel sensors fabricated in 150 nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they offer high production throughput at comparatively low cost. Moreover, several features like poly-silicon resistors, MIM-capacitors and several metal layers are available which can help enhance the sensor design. The performance of a 100 $\mathrmμ$m thin passive CMOS sensor with a pixel pitch of 50 $\mathrmμ$m at different irradiation levels, 5 $\times$ 10$^{15}$n$_{\mathrm{eq}}$cm$^{-2}$ and 1 $\ti…
IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of 16 x 16 pixels CdTe or CdZnTe pixelated detectors to build low power micro gamma camera. IDeF-X HD has been designed in the standard AMS CMOS 0.35 microns process technology. Its power consumption is 800 micro watt per channel. The dynamic range of the ASIC can be extended to 1.1 MeV thanks to the in-channel adjustable gain stage. When no detector is connected to the chip and without input current, a 33 electrons rms ENC level is achieved after shaping with 10.7 micro seconds peak time. Spec…
High Voltage Monolithic Active Pixel Sensors (HV-MAPS) are based on a commercial High Voltage CMOS process and collect charge by drift inside a reversely biased diode. HV-MAPS represent a promising technology for future pixel tracking detectors. Two recent developments are presented. The MuPix has a continuous readout and is being developed for the Mu3e experiment whereas the ATLASPix is being developed for LHC applications with a triggered readout. Both variants have a fully monolithic design including state machines, clock circuitries and serial drivers. Several prototypes and design variant…
High-Voltage Monolithic Active Pixel Sensors (HV-MAPS) based on the 180 nm HV-CMOS process have been proposed to realize thin, fast and highly integrated pixel sensors. The MuPix7 prototype, fabricated in the commercial AMS H18 process, features a fully integrated on-chip readout, i.e. hit-digitization, zero suppression and data serialization. It is the first fully monolithic HV-CMOS pixel sensor that has been tested for the use in high irradiation environments like HL-LHC. We present results from laboratory and test beam measurements of MuPix7 prototypes irradiated with neutrons (up to $5.0\c…
Optical readout of GEM based devices by means of high granularity and low noise CMOS sensors allows to obtain very interesting tracking performance. Space resolution of the order of tens of $μ$m were measured on the GEM plane along with an energy resolution of 20%$÷$30%. The main limitation of CMOS sensors is represented by their poor information about time structure of the event. In this paper, the use of a concurrent light readout by means of a suitable photomultiplier and the acquisition of the electric signal induced on the GEM electrode are exploited to provide the necessary timing inform…
A single-photon CMOS image sensor design based on pinned photodiode (PPD) with multiple charge transfers and sampling is described. In the proposed pixel architecture, the photogenerated signal is sampled non-destructively multiple times and the results are averaged. Each signal measurement is statistically independent and by averaging the electronic readout noise is reduced to a level where single photons can be distinguished reliably. A pixel design using this method has been simulated in TCAD and several layouts have been generated for a 180 nm CMOS image sensor process. Using simulations, …
In the context of the studies of the ATLAS High Luminosity LHC programme, radiation tolerant pixel detectors in CMOS technologies are investigated. To evaluate the effects of substrate resistivity on CMOS sensor performance, the H35DEMO demonstrator, containing different diode and amplifier designs, was produced in ams H35 HV-CMOS technology using four different substrate resistivities spanning from $\mathrm{80}$ to $\mathrm{1000~Ω\cdot cm}$. A glueing process using a high-precision flip-chip machine was developed in order to capacitively couple the sensors to FE-I4 Readout ASIC using a thin l…
Many years of research and development of High Voltage Monolithic Active Pixel Sensors (HVMAPS) have culminated in the final design for the Mu3e pixel sensor. MuPix10 is a fully monolithic sensor with an active pixel matrix size of $20\times20\,\mathrm{mm}^2$ produced in the $180\,\mathrm{nm}$ HV-CMOS process at TSI Semiconductors. The pixel size is $80\times80\,\mathrm{μm}^2$. Hits are read out using a column-drain architecture and sent over up to four serial links with up to $1.6\,\left.\mathrm{Gbit}\middle/\mathrm{s}\right.$ each. By means of DC/DC converters and exclusive usage of on-chip …
The CERN-RD50 CMOS working group develops the RD50-MPWseries of monolithic high-voltage CMOS pixel sensors for potential use in future high luminosity experiments such as the HL-LHC and FCC-hh. In this contribution, the design of the latest prototype in this series, RD50-MPW3, is presented. An overview of its pixel matrix and digital readout periphery is given, with discussion of the new structures implemented in the chip and the problems they aim to solve. The main analog and digital features of the sensor are already tested and initial laboratory characterisation of the chip is presented.
The photon counting imaging paradigm in the visible and the infrared comes from the very small energy carried by a single photon at these wavelengths. Usually to detect photons the photoelectric effect is used. It converts a photon to a single electron making it very difficult to detect because of the readout noise of the electronics. To overcome this there are two strategies, either to amplify the signal to make it larger than the readout noise (used in the so called gain or amplified detectors), or to lower the readout noise in a standard image sensor. For a long time, only amplified detecto…
