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arXiv 2109.01296physics.ins-dethep-ex
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用于CMS端盖定时层读出芯片的像素内自动阈值校准

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

H. Sun, D. Gong, C. Edwards, G. Huang, X. Huang, C. Liu, T. Liu, T. Liu, J. Olsen, Q. Sun, J. Wu, J. Ye, L. Zhang, W. Zhang

摘要:

本文介绍了在高亮度LHC升级中CMS端盖定时层(ETL)的像素内自动阈值校准电路的实现和验证。ETL读出芯片(ETROC)的阈值需要定期校准,以减轻电路基线的变化。传统的方法需要通过缓慢的控制系统进行大量的通信,因此非常耗时。本文介绍了一种像素内的自动化方案,在操作时间和可用性的改进。在该方案中,使用一个采样累积电路来测量平均采样输出。应用二进制逐次逼近和线性组合扫描来找到等效基线。实际的校准过程已首先在FPGA固件中实现,并使用ETROC前端原型芯片(ETROC0)进行测试。校准电路已实现与三模冗余(TMR)和验证与单粒子效应(SEES)模拟。一个完整的校准过程持续35 ms,时钟为40 MHz。在最坏的情况下,动态和静态功耗估计分别为300 uW和10.4 uW。该电路设计采用65 CMOS技术实现,将集成到ETROC 2中,ETROC 2是ETROC的下一个迭代,具有16x16像素矩阵。

英文摘要:

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16x16 pixel matrix.

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