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arXiv 2302.07555physics.ins-detcs.LGhep-ex
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ATLAS实验中用于计算液氩量能器沉积能量的循环神经网络固件实现

Firmware implementation of a recurrent neural network for the computation of the energy deposited in the liquid argon calorimeter of the ATLAS experiment

Aix Marseille Univ(艾克斯-马赛大学);CNRS/IN2P3(法国国家科学研究中心/核物理与粒子物理研究所)

Georges Aad, Thomas Calvet, Nemer Chiedde, Robert Faure, Etienne Marie Fortin, Lauri Laatu, Emmanuel Monnier, Nairit Sur

AI总结:

本文提出了一种在Stratix 10 FPGA上实现RNN的方法,用于ATLAS液氩量能器沉积能量重建,通过VHDL优化满足了每FPGA处理384通道且延迟小于125 ns的严格要求。

摘要:

ATLAS实验测量LHC质子-质子碰撞产生的粒子性质。ATLAS探测器将在LHC高亮度阶段前进行重大升级。ATLAS液氩量能器测量在探测器中发生电磁相互作用的粒子能量。该量能器的读出电子学将在上述ATLAS升级期间被替换。新电子板将基于Intel最先进的现场可编程门阵列(FPGA),允许在固件中嵌入神经网络。已证明神经网络优于当前用于计算量能器中沉积能量的最优滤波算法。本文介绍了在Stratix 10 FPGA上实现循环神经网络(RNN)以重建量能器中沉积能量的方法。使用高层次综合(HLS)语言实现允许快速原型设计,但在资源使用和延迟方面未能满足严格要求。在VHSIC硬件描述语言(VHDL)中的进一步优化满足了每个FPGA处理384个通道且延迟小于125 ns的要求。

英文摘要:

The ATLAS experiment measures the properties of particles that are products of proton-proton collisions at the LHC. The ATLAS detector will undergo a major upgrade before the high luminosity phase of the LHC. The ATLAS liquid argon calorimeter measures the energy of particles interacting electromagnetically in the detector. The readout electronics of this calorimeter will be replaced during the aforementioned ATLAS upgrade. The new electronic boards will be based on state-of-the-art field-programmable gate arrays (FPGA) from Intel allowing the implementation of neural networks embedded in firmware. Neural networks have been shown to outperform the current optimal filtering algorithms used to compute the energy deposited in the calorimeter. This article presents the implementation of a recurrent neural network (RNN) allowing the reconstruction of the energy deposited in the calorimeter on Stratix 10 FPGAs. The implementation in high level synthesis (HLS) language allowed fast prototyping but fell short of meeting the stringent requirements in terms of resource usage and latency. Further optimisations in Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allowed fulfilment of the requirements of processing 384 channels per FPGA with a latency smaller than 125 ns.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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