Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM technology in large Last-Level Caches (LLCs). Despite its high-density, non-volatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache suffers from high error rates mainly due to retention failure, read disturbance, and write failure. Existing studies are limited to estimating the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, which its estimation is a must to design cost-efficient reliable caches, has not been offered in any of previous studies. In this paper, we propose a system-level framework for reliability exploration and characterization of errors behavior in STT-MRAM caches. To this end, we formulate the cache vulnerability considering the inter-correlation of the error types including all three errors as well as the dependency of error rates to workloads behavior and Process Variations (PVs). Our analysis reveals that STT-MRAM cache vulnerability is highly workload-dependent and varies by orders of magnitude in different cache access patterns. Our analytical study also shows that this vulnerability divergence significantly increases by process variations in STT-MRAM cells. To evaluate the framework, we implement the error types in the gem5 full-system simulator, and the experimental results show that the total error rate in a shared LLC varies by 32.0x for different workloads. A further 6.5x vulnerability variation is observed when considering PVs in the STT-MRAM cells. In addition, the contribution of each error type in total LLC vulnerability highly varies in different cache access patterns and moreover, error rates are differently affected by PVs.
Reuse Distance-based Copy-backs of Clean Cache Lines to Lower-level Caches
缓存在缩小CPU和主存之间的性能差距方面起着至关重要的作用。现代多核CPU通常采用多级缓存层次结构，通过该结构，最近和频繁使用的数据被维护在每个核的本地私有缓存中，而所有核共享最后一级缓存（LLC）。对于包含性高速缓存，在较高级别高速缓存中替换的干净高速缓存行不一定被复制回较低级别，因为包含性意味着它们存在于较低级别中。对于当今被Intel、AMD和ARM广泛使用的独占和非包含高速缓存，不加区别地将所有或不将替换的干净高速缓存行复制回较低级别不会违反独占性和非包含性定义。我们已经进行了定量研究，并发现，复制回所有或没有干净的高速缓存线，以较低级别的高速缓存的排他缓存需要次优的性能。其原因是，只有一部分缓存线将被重用，而其他人变成死在长期运行。这种观察促使我们选择性地将一些干净的高速缓存行复制回独占或非独占高速缓存架构中的LLC。我们重新讨论了高速缓存线的重用距离的概念。简而言之，具有较短重用距离的干净高速缓存行被复制回较低级别高速缓存，因为它可能在不久的将来被重新引用，而具有长得多的重用距离的高速缓存行将被丢弃或发送到存储器，如果它们是脏的。我们已经实施和评估了我们的建议与非易失性（STT-MRAM）有限责任公司。使用gem 5和SPEC CPU 2017基准测试的实验结果表明，平均而言，我们的建议比最近最少使用（LRU）替换策略（为STT-MRAM LLC复制所有干净的高速缓存行…
HyGain: High Performance, Energy-Efficient Hybrid Gain Cell based Cache Hierarchy
在本文中，我们提出了一个“全栈”的解决方案，设计高容量和低延迟的片上高速缓存层次结构的硬件设计栈的电路级开始。首先，我们提出了一种新颖的增益单元（GC）的设计使用FDSOI。GC具有几个理想的特性，包括与传统的6 T SRAM相比，存储密度高约50%，动态能量低约50%，即使在考虑外围电路开销之后。我们还利用背栅偏置将保留时间提高到1.12 ms（约为eDRAM的60倍），结合交错刷新等优化，使其成为构建各级片上缓存的理想候选者。我们表明，与6 T SRAM相比，对于给定的面积预算，基于GC的缓存平均为单编程和多编程工作负载分别提供29%和36%的IPC增加，包括SPEC CPU 2017在内的当代工作负载。我们还观察到，单编程和多编程工作负载的动态节能分别为42%和34%。我们利用所提出的GC的固有属性，包括解耦的读和写位线设计优化，以节省预充电能量和建筑GC缓存具有更好的能量和性能特性。最后，为了利用所有世界中最好的东西，我们将GC与STT-RAM结合起来创建混合层次结构。我们表明，在L1和L2的GC缓存的混合层次结构，和GC和STT-RAM之间的LLC分裂，启用非对称写入优化，能够提供54%的好处，在能量延迟产品（EDP）相比，全SRAM设计，和13%相比，全GC缓存层次结构，平均跨多编程的工作负载。
