多核系统中密集型非易失性缓存的性能和功耗效率研究
A Study on Performance and Power Efficiency of Dense Non-Volatile Caches in Multi-Core Systems
摘要：
在本文中，我们提出了一种新的高速缓存设计的多级单元自旋转移力矩RAM（MLC STTRAM）的基础上，可以动态地适应设置容量和关联有效地使用MLC STTRAM的全部潜力。我们利用MLC存储方案的非对称性来构建具有异构性能的高速缓存行，即，一半的高速缓存行是读友好的，而另一半是写友好的。此外，我们建议在未充分利用的集合中机会性地停用方法，以将MLC转换为单级单元（SLC）模式，该模式具有整体更好的性能和寿命。我们的最终目标是建立一个缓存架构，结合MLC的容量优势和SLC的性能/能源优势。我们的实验表明，冲突未命中总数的43%，27%的内存访问延迟，12%的系统性能，和26%的LLC访问能量的改善，缓存寿命略有下降（约7%）相比，SLC缓存。
英文摘要：
In this paper, we present a novel cache design based on Multi-Level Cell Spin-Transfer Torque RAM (MLC STTRAM) that can dynamically adapt the set capacity and associativity to use efficiently the full potential of MLC STTRAM. We exploit the asymmetric nature of the MLC storage scheme to build cache lines featuring heterogeneous performances, that is, half of the cache lines are read-friendly, while the other is write-friendly. Furthermore, we propose to opportunistically deactivate ways in underutilized sets to convert MLC to Single-Level Cell (SLC) mode, which features overall better performance and lifetime. Our ultimate goal is to build a cache architecture that combines the capacity advantages of MLC and performance/energy advantages of SLC. Our experiments show an improvement of 43% in total numbers of conflict misses, 27% in memory access latency, 12% in system performance, and 26% in LLC access energy, with a slight degradation in cache lifetime (about 7%) compared to an SLC cache.
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