利用五层菱方石墨烯的铁谷电性实现存储与计算
Harnessing Ferro-Valleytricity in Penta-Layer Rhombohedral Graphene for Memory and Compute
AI总结：
本文利用五层菱方石墨烯的电可调铁谷电性，提出无需选择器的非易失性存储器阵列架构，实现每单元写约6 nW、读约2.3 nW的超低功耗，并在不修改外围电路的情况下实现多数逻辑存内计算，为超密集低温存储与计算提供新路径。
摘要：
具有自旋、谷和轨道等多自由度的二维材料为设计多功能器件开辟了令人振奋的途径。超越自旋电子学，这些自由度可以催生诸如谷依赖霍尔效应和轨道磁性等新奇量子效应，有望革新下一代电子学。然而，由于需要大电场，独立控制谷极化和轨道磁性一直是一个挑战。最近一项涉及五层菱方石墨烯的突破性工作展示了分别操纵反常霍尔信号和轨道磁滞回线的能力，形成了所谓的谷-磁四重态。在此，我们利用五层菱方石墨烯的电可调铁谷电性来开发非易失性存储器和存内计算应用。我们提出了一种密集、可扩展且无需选择器的非易失性存储器阵列架构，该架构利用电可调的铁谷电性。在我们设计的阵列架构中，非破坏性读写操作通过两对不同端子感测谷态来进行，从而允许独立优化读写外围电路。我们基于五层菱方石墨烯（PRG）的阵列功耗极低，每个单元每次写操作仅需约6 nW，每次读操作仅需约2.3 nW。这一功耗比大多数最先进的低温存储器低数个数量级。此外，我们在所提出的非易失性存储器阵列中通过实现多数逻辑运算来构建存内计算，且无需修改外围电路。我们的框架为实现超密集低温存储器和存内计算能力提供了一条有前景的路径。
英文摘要：
Two-dimensional materials with multiple degrees of freedom, including spin, valleys, and orbitals, open up an exciting avenue for engineering multifunctional devices. Beyond spintronics, these degrees of freedom can lead to novel quantum effects such as valley-dependent Hall effects and orbital magnetism, which could revolutionize next-generation electronics. However, achieving independent control over valley polarization and orbital magnetism has been a challenge due to the need for large electric fields. A recent breakthrough involving penta-layer rhombohedral graphene has demonstrated the ability to individually manipulate anomalous Hall signals and orbital magnetic hysteresis, forming what is known as a valley-magnetic quartet. Here, we leverage the electrically tunable Ferro-valleytricity of penta-layer rhombohedral graphene to develop non-volatile memory and in-memory computation applications. We propose an architecture for a dense, scalable, and selector-less non-volatile memory array that harnesses the electrically tunable ferro-valleytricity. In our designed array architecture, non-destructive read and write operations are conducted by sensing the valley state through two different pairs of terminals, allowing for independent optimization of read/write peripheral circuits. The power consumption of our PRG-based array is remarkably low, with only ~ 6 nW required per write operation and ~ 2.3 nW per read operation per cell. This consumption is orders of magnitude lower than that of the majority of state-of-the-art cryogenic memories. Additionally, we engineer in-memory computation by implementing majority logic operations within our proposed non-volatile memory array without modifying the peripheral circuitry. Our framework presents a promising pathway toward achieving ultra-dense cryogenic memory and in-memory computation capabilities.
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