构造非易失性主存以防范持久性攻击
Architecting Non-Volatile Main Memory to Guard Against Persistence-based Attacks
摘要：
基于DRAM的主存储器及其相关组件越来越多地占计算生态系统内应用性能瓶颈和功率预算需求的很大一部分。为了缓解与DRAM相关联的存储密度和功率限制的问题，系统架构师正在研究替代非易失性存储器技术，例如相变存储器（PCM），以替代DRAM存储器或与DRAM存储器一起使用。虽然这种替代存储器类型提供了克服DRAM相关问题的许多承诺，但由于即使在断电后存储器数据的持久性，它们也对用户构成了重大的安全威胁。在本文中，我们研究智能机制，以掩盖掉电后留在非易失性存储器中的数据。特别是，我们分析了使用单一的加密算法与差分加密的应用程序阶段的安全需求的基础上的效果。我们还探讨了混合主存储器，有一个DRAM缓冲区高速缓存加上PCM主存储器上的加密效果。我们的机制考虑到有限的写入耐久性问题与几个非易失性存储器技术，包括PCM，并避免任何额外的写入超出最初发出的应用程序。我们使用Gem5模拟器和SPEC 2006应用程序进行评估，并显示我们所提出的设计的性能和功耗开销。
英文摘要：
DRAM-based main memory and its associated components increasingly account for a significant portion of application performance bottlenecks and power budget demands inside the computing ecosystem. To alleviate the problems of storage density and power constraints associated with DRAM, system architects are investigating alternative non-volatile memory technologies such as Phase Change Memory (PCM) to either replace or be used alongside DRAM memory. While such alternative memory types offer many promises to overcome the DRAM-related issues, they present a significant security threat to the users due to persistence of memory data even after power down. In this paper, we investigate smart mechanisms to obscure the data left in non-volatile memory after power down. In particular, we analyze the effect of using a single encryption algorithm versus differentiated encryption based on the security needs of the application phases. We also explore the effect of encryption on a hybrid main memory that has a DRAM buffer cache plus PCM main memory. Our mechanism takes into account the limited write endurance problem associated with several non-volatile memory technologies including PCM, and avoids any additional writes beyond those originally issued by the applications. We evaluate using Gem5 simulator and SPEC 2006 applications, and show the performance and power overheads of our proposed design.
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