DeepNVM ++：面向深度学习的非易失性存储器跨层建模与优化框架
DeepNVM++: Cross-Layer Modeling and Optimization Framework of Non-Volatile Memories for Deep Learning
摘要：
非易失性存储器（NVM）技术（诸如自旋转移矩磁性随机存取存储器（STT-MRAM）和自旋轨道矩磁性随机存取存储器（SOT-MRAM））由于其非易失性、更高的单元密度和可缩放性特征而与常规SRAM相比具有显著的优点。虽然以前的工作已经研究了NVM对通用应用程序的几种架构影响，但在这项工作中，我们提出了DeepNVM++，这是一个框架，通过结合技术特定的电路级模型和各种DL工作负载的实际内存行为，来表征，建模和分析GPU架构中基于NVM的缓存，用于深度学习（DL）应用程序。我们提出了等容量和等面积的性能和能量分析系统的最后一级缓存依赖于传统的SRAM和新兴的STT-MRAM和SOT-MRAM技术。在等容量情况下，与传统SRAM相比，STT-MRAM和SOT-MRAM分别提供高达3.8倍和4.7倍的能量延迟乘积（EDP）减少以及2.4倍和2.8倍的面积减少。在等面积假设下，与SRAM相比，STT-MRAM和SOT-MRAM分别提供高达2倍和2.3倍的EDP减少，并容纳2.3倍和3.3倍的缓存容量。我们还进行了可扩展性分析，并表明，STT-MRAM和SOT-MRAM实现的数量级EDP减少相比，SRAM的大缓存容量。我们全面的跨层框架在STT-/SOT-MRAM技术上得到了演示，可用于DL应用中GPU末级缓存的任何NVM技术的表征、建模和分析。
英文摘要：
Non-volatile memory (NVM) technologies such as spin-transfer torque magnetic random access memory (STT-MRAM) and spin-orbit torque magnetic random access memory (SOT-MRAM) have significant advantages compared to conventional SRAM due to their non-volatility, higher cell density, and scalability features. While previous work has investigated several architectural implications of NVM for generic applications, in this work we present DeepNVM++, a framework to characterize, model, and analyze NVM-based caches in GPU architectures for deep learning (DL) applications by combining technology-specific circuit-level models and the actual memory behavior of various DL workloads. We present both iso-capacity and iso-area performance and energy analysis for systems whose last-level caches rely on conventional SRAM and emerging STT-MRAM and SOT-MRAM technologies. In the iso-capacity case, STT-MRAM and SOT-MRAM provide up to 3.8x and 4.7x energy-delay product (EDP) reduction and 2.4x and 2.8x area reduction compared to conventional SRAM, respectively. Under iso-area assumptions, STT-MRAM and SOT-MRAM provide up to 2x and 2.3x EDP reduction and accommodate 2.3x and 3.3x cache capacity when compared to SRAM, respectively. We also perform a scalability analysis and show that STT-MRAM and SOT-MRAM achieve orders of magnitude EDP reduction when compared to SRAM for large cache capacities. Our comprehensive cross-layer framework is demonstrated on STT-/SOT-MRAM technologies and can be used for the characterization, modeling, and analysis of any NVM technology for last-level caches in GPUs for DL applications.
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