混合分层存储器中利用存储器间和存储器内的不对称性进行数据映射
Exploiting Inter- and Intra-Memory Asymmetries for Data Mapping in Hybrid Tiered-Memories
摘要：
现代计算系统正在采用由DRAM和非易失性存储器（NVM）组成的混合存储器，以组合两种存储器技术的最佳特性，从而实现低延迟、高可靠性和高密度。DRAM-NVM混合存储器的一个突出特征是其NVM访问延迟比DRAM访问延迟高得多。我们称之为记忆间不对称。我们观察到，寄生组件上的一个长的DRAM和NVM中的高延迟的主要来源，并在NVM中，这影响其可靠性的高电压操作的一个重要因素。我们提出了一个架构的变化，在DRAM和NVM中的每个长存储器被分成两个部分的隔离晶体管。一个段可以以比另一个段更低的延迟和工作电压被访问。通过引入层，我们使每个存储器类型内的非均匀访问（我们称之为内存内不对称），导致性能和可靠性的DRAM-NVM混合存储器的权衡。我们以三种方式扩展现有的NVM-DRAM操作系统。首先，我们利用内存间和内存内的不对称性来分配和迁移DRAM和NVM层之间的内存页面。其次，我们通过预测程序中新引用的内存页面的访问强度并在初始分配期间将其放置到匹配层来改进操作系统的页面分配决策。这最大限度地减少了程序执行期间的页面迁移，降低了性能开销。第三，我们提出了一个解决方案，在同一内存的层之间迁移页面，而不通过内存通道传输数据，最大限度地减少通道占用，提高性能。我们的整体方法，我们称之为MNEME，启用和利用DRAM-NVM混合分层存储器中的不对称性，提高了单核和多编程工作负载的性能和可靠性。
英文摘要：
Modern computing systems are embracing hybrid memory comprising of DRAM and non-volatile memory (NVM) to combine the best properties of both memory technologies, achieving low latency, high reliability, and high density. A prominent characteristic of DRAM-NVM hybrid memory is that it has NVM access latency much higher than DRAM access latency. We call this inter-memory asymmetry. We observe that parasitic components on a long bitline are a major source of high latency in both DRAM and NVM, and a significant factor contributing to high-voltage operations in NVM, which impact their reliability. We propose an architectural change, where each long bitline in DRAM and NVM is split into two segments by an isolation transistor. One segment can be accessed with lower latency and operating voltage than the other. By introducing tiers, we enable non-uniform accesses within each memory type (which we call intra-memory asymmetry), leading to performance and reliability trade-offs in DRAM-NVM hybrid memory. We extend existing NVM-DRAM OS in three ways. First, we exploit both inter- and intra-memory asymmetries to allocate and migrate memory pages between the tiers in DRAM and NVM. Second, we improve the OS's page allocation decisions by predicting the access intensity of a newly-referenced memory page in a program and placing it to a matching tier during its initial allocation. This minimizes page migrations during program execution, lowering the performance overhead. Third, we propose a solution to migrate pages between the tiers of the same memory without transferring data over the memory channel, minimizing channel occupancy and improving performance. Our overall approach, which we call MNEME, to enable and exploit asymmetries in DRAM-NVM hybrid tiered memory improves both performance and reliability for both single-core and multi-programmed workloads.
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