用于吞吐量和能量增强的读调谐STT-RAM和eDRAM缓存层次结构
Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Enhancement
摘要：
随着片上高速缓存存储层次结构的容量和复杂度的增加，最后一级高速缓存（LLC）对频繁重复的关键负载的服务成本已成为一个主要问题。如果没有独立的指令要执行，则处理器在等待访问存储在LLC中的高速缓存块中的数据时可能会停顿相当长的时间间隔。为了提供加速服务的关键负载请求从LLC，这项工作集中在利用额外的容量，取代基于SRAM的L2自旋转移扭矩随机存取存储器（STT-RAM），以适应频繁访问的高速缓存块在独占读取模式，有利于减少整体读取服务时间。我们提出的技术分区L2缓存到两个STT-RAM的安排，具有不同的写性能和数据保留时间。保留放松的STT-RAM阵列被用来有效地处理常规的L2高速缓存请求，而L2中的高保留STT-RAM阵列被选择用于通过引起用于数据保留的可忽略的能量消耗来维持来自LLC的重复读取访问的高速缓存块。我们的实验结果表明，所提出的技术可以降低平均L2读未命中率的51.4%，平均增加11.7%的IPC在PARSEC基准套件，同时显着降低总L2的能源消耗相比，传统的基于SRAM的L2设计。
英文摘要：
As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from Last Level Cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a considerable interval while waiting to access the data stored in the cache blocks in LLC, if there are no independent instructions to execute. To provide accelerated service to the critical loads requests from LLC, this work concentrates on leveraging the additional capacity offered by replacing SRAM-based L2 with Spin-Transfer Torque Random Access Memory (STT-RAM) to accommodate frequently accessed cache blocks in exclusive read mode in favor of reducing the overall read service time. Our proposed technique partitions L2 cache into two STT-RAM arrangements with different write performance and data retention time. The retention-relaxed STT-RAM arrays are utilized to effectively deal with the regular L2 cache requests while the high retention STT-RAM arrays in L2 are selected for maintaining repeatedly read accessed cache blocks from LLC by incurring negligible energy consumption for data retention. Our experimental results show that the proposed technique can reduce the mean L2 read miss ratio by 51.4% and increase the IPC by 11.7% on average across PARSEC benchmark suite while significantly decreasing the total L2 energy consumption compared to conventional SRAM-based L2 design.
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