Reuse Detector：改进STT-RAM SLLC的管理
Reuse Detector: Improving the Management of STT-RAM SLLCs
AI总结：
针对STT-RAM SLLC写入慢、能耗高的问题，提出加入Reuse Detector检测无重用缓存块以避免插入的管理机制，相比现有最优方案DASCA，在能耗降低和性能提升上均更具优势。
摘要：
静态随机存取存储器（SRAM）的各类限制促使研究人员探索新型存储技术，以作为构建片上共享末级缓存（SLLC）的候选方案。自旋转移矩随机存取存储器（STT-RAM）凭借更优的能效、更小的芯片占用面积和更强的可扩展性，目前被认为是首要的备选技术。然而STT-RAM也存在写入操作速度慢、能耗高的缺陷，亟需得到缓解。\n本研究通过提出一种新型STT-RAM SLLC管理机制来解决上述不足。该方法基于此前的观测结论：到达芯片多处理器（CMP）SLLC的引用流具有重用局部性，即被多次引用的缓存块有很高概率会在未来被再次重用。本文采用的缓存管理机制选择SLLC的内容时，旨在利用重用局部性而非时间局部性。具体而言，我们的方案是在私有缓存层级与STT-RAM SLLC之间加入一个Reuse Detector（重用检测器），用于检测不具备重用特性的缓存块，避免将它们插入SLLC，从而减少STT-RAM的写入操作次数并降低能耗。\n我们的评估结果显示，与未采用重用检测器的STT-RAM SLLC基准方案相比，该方案平均可使SLLC能耗降低37%-30%，主存能耗额外降低6%-8%，在16核配置下性能提升3%至14%。更重要的是，我们的方法优于当前最先进的STT-RAM SLLC管理方案DASCA：其SLLC能耗节省幅度比DASCA高4%-11%，性能提升幅度比DASCA高1.5%-14%，DRAM能耗的额外降低幅度也比DASCA高2%-9%。
英文摘要：
Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the prime contender due to its better energy efficiency, smaller die footprint and higher scalability. However, STT-RAM also exhibits some drawbacks, like slow and energy-hungry write operations, that need to be mitigated. In this work we address these shortcomings by leveraging a new management mechanism for STT-RAM SLLCs. This approach is based on the previous observation that the stream of references arriving at the SLLC of a Chip MultiProcessor (CMP) exhibits reuse locality, i.e., those blocks referenced several times manifest high probability of forthcoming reuse. In this paper, we employ a cache management mechanism that selects the contents of the SLLC aimed to exploit reuse locality instead of temporal locality. Specifically, our proposal consists in the inclusion of a Reuse Detector between private cache levels and the STT-RAM SLLC to detect blocks that do not exhibit reuse, in order to avoid their insertion in the SLLC, hence reducing the number of write operations and the energy consumption in the STT-RAM. Our evaluation reveals that our scheme reports on average, energy reductions in the SLLC in the range of 37-30\%, additional energy savings in the main memory in the range of 6-8\% and performance improvements of 3\% up to 14\% (16-core) compared to an STT-RAM SLLC baseline where no reuse detector is employed. More importantly, our approach outperforms DASCA, the state-of-the-art STT-RAM SLLC management, reporting SLLC energy savings in the range of 4-11\% higher than those of DASCA, delivering higher performance in the range of 1.5-14\%, and additional improvements in DRAM energy consumption in the range of 2-9\% higher than DASCA.
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