SCART：使用机器学习预测STT-RAM缓存保持时间
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning
AI总结：
本文提出SCART模型，利用机器学习基于易获取的SRAM统计信息预测STT-RAM缓存的保持时间，以最小化探索开销并优化延迟与能耗，实验显示其能显著降低延迟、能耗及探索开销。
摘要：
先前的研究表明，可以放宽非易失性自旋转移矩RAM（STT-RAM）的保持时间，以降低STT-RAM的写入能耗和延迟。然而，由于不同的应用程序可能需要不同的保持时间，因此必须严格探索STT-RAM的保持时间以满足各种应用程序的需求。由于探索开销，这一过程可能具有挑战性，并且由于STT-RAM缓存是新兴技术，无法随时用于设计时探索，这一事实加剧了该挑战。本文探索使用已知且易于获取的统计信息（例如SRAM统计信息）来预测合适的STT-RAM保持时间，以最小化探索开销。我们提出了一个STT-RAM缓存保持时间（SCART）模型，该模型利用机器学习来实现对延迟或能耗优化的、适当配置的STT-RAM保持时间的设计时或运行时预测。实验结果表明，与同质保持时间相比，SCART平均可分别减少20.34%的延迟和29.12%的能耗，同时与先前工作相比减少了52.58%的探索开销。
英文摘要：
Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM's write energy and latency. However, since different applications may require different retention times, STT-RAM retention times must be critically explored to satisfy various applications' needs. This process can be challenging due to exploration overhead, and exacerbated by the fact that STT-RAM caches are emerging and are not readily available for design time exploration. This paper explores using known and easily obtainable statistics (e.g., SRAM statistics) to predict the appropriate STT-RAM retention times, in order to minimize exploration overhead. We propose an STT-RAM Cache Retention Time (SCART) model, which utilizes machine learning to enable design time or runtime prediction of right-provisioned STT-RAM retention times for latency or energy optimization. Experimental results show that, on average, SCART can reduce the latency and energy by 20.34% and 29.12%, respectively, compared to a homogeneous retention time while reducing the exploration overheads by 52.58% compared to prior work.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
