TA-LRW：一种降低STT-MRAM缓存出错率的替换策略
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches
摘要：
随着工艺节点规模的缩小，片上SRAM高速缓存由于其低可扩展性、高泄漏功率和增加的软错误率而失去其效率。在新兴的存储器技术中，自旋转移力矩磁性RAM（STT-MRAM）被认为是基于SRAM的高速缓存存储器的最有前途的替代品。STT-MRAM的主要优点是其非易失性、接近零的泄漏功率、更高的密度、软错误免疫性和更高的可扩展性。尽管有这些优点，但由于保持故障、写入故障及读取干扰而导致的STT-MRAM单元中的高出错率威胁到建立于STT-MRAM技术上的高速缓冲存储器的可靠性。出错率在较高温度下显著增加，这进一步影响基于STT-MRAM的高速缓冲存储器的可靠性。STT-MRAM高速缓冲存储器中的热生成和温度升高的主要来源是写入操作，其由高速缓存替换策略管理。在本文中，我们首先分析了传统的LRU替换策略中的高速缓存行为，并证明了大多数连续的写操作（超过66%）都被提交到相邻的高速缓存块。这些相邻的写操作会导致热量累积和温度升高，从而显著增加高速缓存出错率。为了消除热量积累和相邻的连续写入，我们提出了一个缓存替换策略，命名为热感知最近写（TA-LRW），通过在遥远的缓存块进行连续的写操作，顺利地分配所产生的热量。TA-LRW保证8路关联缓存中每两个连续写操作至少有三个块的距离。与传统LRU策略相比，这种远程写入方案将温度引起的出错率平均降低了94.8%，这导致高速缓存出错率降低了6.9倍。
英文摘要：
As technology process node scales down, on-chip SRAM caches lose their efficiency because of their low scalability, high leakage power, and increasing rate of soft errors. Among emerging memory technologies, Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM-based cache memories. The main advantages of STT-MRAM are its non-volatility, near-zero leakage power, higher density, soft-error immunity, and higher scalability. Despite these advantages, the high error rate in STT-MRAM cells due to retention failure, write failure, and read disturbance threatens the reliability of cache memories built upon STT-MRAM technology. The error rate is significantly increased in higher temperatures, which further affects the reliability of STT-MRAM-based cache memories. The major source of heat generation and temperature increase in STT-MRAM cache memories is write operations, which are managed by cache replacement policy. In this paper, we first analyze the cache behavior in the conventional LRU replacement policy and demonstrate that the majority of consecutive write operations (more than 66%) are committed to adjacent cache blocks. These adjacent write operations cause accumulated heat and increased temperature, which significantly increases the cache error rate. To eliminate heat accumulation and the adjacency of consecutive writes, we propose a cache replacement policy, named Thermal-Aware Least-Recently Written (TA-LRW), to smoothly distribute the generated heat by conducting consecutive write operations in distant cache blocks. TA-LRW guarantees the distance of at least three blocks for each two consecutive write operations in an 8-way associative cache. This distant write scheme reduces the temperature-induced error rate by 94.8%, on average, compared with the conventional LRU policy, which results in 6.9x reduction in cache error rate.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
