用定制的STT-MRAM设计高效、高性能的AI加速器
Designing Efficient and High-performance AI Accelerators with Customized STT-MRAM
摘要：
在本文中，我们展示了高效和高性能的AI/深度学习加速器的设计与定制的STT-MRAM和可重新配置的核心。基于模型驱动的详细设计空间探索，我们提出了一种创新的暂存器辅助片上STT-MRAM的高性能加速器的缓冲系统的设计方法。使用AI模型权重和激活图的存储器占用时间的解析导出的表达式，STT-MRAM的易失性利用热稳定性因子的工艺和温度变化感知缩放来调整，以优化STT-MRAM的保留时间、能量、读/写延迟和面积。通过分析现代AI工作负载和14 nm技术中的加速器实现，我们验证了我们设计的STT-MRAM STT-AI AI加速器的有效性。与基于SRAM的实现相比，STT-AI加速器在等精度下实现了75%的面积和3%的功耗节省。此外，与宽松的位出错率和可忽略的AI精度权衡，所设计的STT-AI超加速器实现了75.4%，和3.5%的节省面积和功率，分别超过常规的基于SRAM的加速器。
英文摘要：
In this paper, we demonstrate the design of efficient and high-performance AI/Deep Learning accelerators with customized STT-MRAM and a reconfigurable core. Based on model-driven detailed design space exploration, we present the design methodology of an innovative scratchpad-assisted on-chip STT-MRAM based buffer system for high-performance accelerators. Using analytically derived expression of memory occupancy time of AI model weights and activation maps, the volatility of STT-MRAM is adjusted with process and temperature variation aware scaling of thermal stability factor to optimize the retention time, energy, read/write latency, and area of STT-MRAM. From the analysis of modern AI workloads and accelerator implementation in 14nm technology, we verify the efficacy of our designed AI accelerator with STT-MRAM STT-AI. Compared to an SRAM-based implementation, the STT-AI accelerator achieves 75% area and 3% power savings at iso-accuracy. Furthermore, with a relaxed bit error rate and negligible AI accuracy trade-off, the designed STT-AI Ultra accelerator achieves 75.4%, and 3.5% savings in area and power, respectively over regular SRAM-based accelerators.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
