arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2007.10702cs.AR
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TCIM:采用MRAM内处理架构的三角形计数加速

TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture

Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao

摘要:

三角形计数(Triangle Counting,TC)是图形分析中的一个基本问题,在GPU和FPGA等传统计算平台上有着广泛的应用。然而,这些方法遭受带宽瓶颈,因为TC计算涉及大量的数据传输。在本文中,我们建议克服这一挑战,设计一个TC加速器利用新兴的处理MRAM(PIM)架构。我们的方法背后的真正创新是一种新颖的方法来执行TC与逐位逻辑运算(如\texttt{AND}),而不是传统的方法,如矩阵计算。这使得高效的存储器中实现TC计算,我们在本文中证明与计算自旋转移矩磁性RAM(STT-MRAM)阵列。此外,我们开发了定制的图切片和映射技术,以加快计算速度,降低能耗。我们使用设备到架构的协同仿真框架来验证我们提出的TC加速器。实验结果表明,该数据映射策略可以减少计算量$99.99\%$和内存操作\texttt{WRITE}的$72\%$。与现有的GPU或FPGA加速器相比,我们的内存加速器分别实现了$9\times$和$23.4\times$的加速,以及比FPGA加速器更高的$20.6\times$能效。

英文摘要:

Triangle counting (TC) is a fundamental problem in graph analysis and has found numerous applications, which motivates many TC acceleration solutions in the traditional computing platforms like GPU and FPGA. However, these approaches suffer from the bandwidth bottleneck because TC calculation involves a large amount of data transfers. In this paper, we propose to overcome this challenge by designing a TC accelerator utilizing the emerging processing-in-MRAM (PIM) architecture. The true innovation behind our approach is a novel method to perform TC with bitwise logic operations (such as \texttt{AND}), instead of the traditional approaches such as matrix computations. This enables the efficient in-memory implementations of TC computation, which we demonstrate in this paper with computational Spin-Transfer Torque Magnetic RAM (STT-MRAM) arrays. Furthermore, we develop customized graph slicing and mapping techniques to speed up the computation and reduce the energy consumption. We use a device-to-architecture co-simulation framework to validate our proposed TC accelerator. The results show that our data mapping strategy could reduce $99.99\%$ of the computation and $72\%$ of the memory \texttt{WRITE} operations. Compared with the existing GPU or FPGA accelerators, our in-memory accelerator achieves speedups of $9\times$ and $23.4\times$, respectively, and a $20.6\times$ energy efficiency improvement over the FPGA accelerator.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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