This technical note presents the design of a new area optimized asynchronous early output dual-bit full adder (DBFA). An asynchronous ripple carry adder (RCA) is constructed based on the new asynchronous DBFAs and existing asynchronous early output single-bit full adders (SBFAs). The asynchronous DBFAs and SBFAs incorporate redundant logic and are encoded using the delay-insensitive dual-rail code (i.e. homogeneous data encoding) and follow a 4-phase return-to-zero handshaking. Compared to the previous asynchronous RCAs involving DBFAs and SBFAs, which are based on homogeneous or heterogeneous delay-insensitive data encodings and which correspond to different timing models, the early output asynchronous RCA incorporating the proposed DBFAs and/or SBFAs is found to result in reduced area for the dual-operand addition operation and feature significantly less latency than the asynchronous RCAs which consist of only SBFAs. The proposed asynchronous DBFA requires 28.6% less silicon than the previously reported asynchronous DBFA. For a 32-bit asynchronous RCA, utilizing 2 stages of SBFAs in the least significant positions and 15 stages of DBFAs in the more significant positions leads to optimization in the latency. The new early output 32-bit asynchronous RCA containing DBFAs and SBFAs reports the following optimizations in design metrics over its counterparts: i) 18.8% reduction in area than a previously reported 32-bit early output asynchronous RCA which also has 15 stages of DBFAs and 2 stages of SBFAs, ii) 29.4% reduction in latency than a 32-bit early output asynchronous RCA containing only SBFAs.
Design and Implementation of an Improved Carry Increment Adder
一种复杂的数字电路，它以加法器为基本单元。电路的性能取决于这个基本加法器单元的设计。电路的运算速度是许多数字电路的重要性能指标之一，它最终取决于基本加法器单元的延迟。许多研究工作致力于改善加法器电路的延迟。在本文中，我们提出了一种改进的进位增量加法器（CIA），提高了电路的延迟性能。在CIA的设计中加入了进位查找加法器（CLA），与以往CIA设计中采用的纹波进位加法器（RCA）不同。进行了仿真研究进行比较分析。采用Verilog硬件描述语言（HDL）进行编码，并在Xilinx ISE 13.1环境下进行仿真。
