基于延迟不敏感双轨数据编码的延迟优化异步超前输出纹波进位加法器
Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding
摘要：
采用延迟不敏感码进行数据表示（即编码）并遵循4相归零协议进行握手的异步电路通常是鲁棒的。根据是否使用单个延迟不敏感代码或多个延迟不敏感代码进行数据编码，编码方案被称为同构或异构延迟不敏感数据编码。本文提出了一种新的延迟优化早期输出异步纹波进位加法器（RCA），它采用了一位异步全加器（SAFA）和双位异步全加器（DAFA），它们采用了冗余逻辑，基于对延迟不敏感的双轨码，即同构数据编码，并遵循4相归零握手。在各种RCA，超前进位加法器（CLA），和进位选择加法器（CSLA）的设计，这是基于同构或异构的延迟不敏感的数据编码，对应于弱指示或早期输出时序模型，所提出的早期输出异步RCA，结合SAFA和DAFA与冗余逻辑被发现，以减少延迟的双操作数加法运算。特别地，对于32位异步RCA，利用15级DAFA和2级SAFA导致减少的延迟。考虑32/28 nm CMOS数字单元库的典型门延迟，计算了不同异步加法器的理论最坏情况延迟，并与实际最坏情况延迟进行了比较。理论和实际最差情况下的延迟显示出密切的相关性......
英文摘要：
Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry adder (RCA) that utilizes single-bit asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA), and carry select adder (CSLA) designs, which are based on homogeneous or heterogeneous delay-insensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dual-operand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation....
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
