速度和能量优化的准延迟不敏感块超前进位加法器
Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder
摘要：
我们提出了一种新的具有冗余进位的异步准延迟不敏感（QDI）块超前进位加法器（BCLARC），使用延迟不敏感的双轨数据编码和4相归零（RTZ）和4相归零（RTZ）实现-到一（RTO）握手。发现所提出的QDI BADOC比现有的异步加法器（其是QDI和非QDI（即，相对定时）。与现有的异步加法器对应的各种架构，如纹波进位加法器（RCA），传统的进位前瞻加法器（CCLA），进位选择加法器（CSLA），BADOC，和混合BADOC-RCA相比，所提出的BADOC被发现是更快，更节能。循环时间（CT）是正向和反向延迟的总和，决定了速度;平均功耗和循环时间的乘积，即功率循环时间乘积（PCTP）定义了低功率/能量效率。对于32位加法，当考虑RTZ和RTO握手时，所提出的QDI BADOC在设计指标上实现了以下平均减少：i）与最佳QDI早期输出RCA相比，CT和PCTP分别减少20.5%和19.6%，ii）与最佳相对定时RCA相比，CT和PCTP分别减少16.5%和15.8%，iii）与最优均匀输入划分QDI早期输出CSLA相比，CT和PCTP分别减少32.9%和35.9%，iv）与最优QDI早期输出CCLA相比，CT和PCTP分别减少47.5%和47.2%，和vi）与最佳QDI早期输出混合物BECHIC-RCA相比，CT和PCTP分别减少12.2%和11.6%。加法器采用32/28 nm CMOS工艺实现。
英文摘要：
We present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundancy carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as ripple carry adder (RCA), conventional carry lookahead adder (CCLA), carry select adder (CSLA), BCLARC, and hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimised. The cycle time (CT), which is the sum of forward and reverse latencies, governs the speed; and the product of average power dissipation and cycle time viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following average reductions in design metrics over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.
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