16 nm FinFET 技术中正反馈绝热逻辑的功率时钟波形评估
Evaluation of Power-Clock Waveforms for Positive Feedback Adiabatic Logic in 16 nm FinFET Technology
浏览论文内容
中文总结 AI 辅助
本研究在 16 nm FinFET 工艺中评估 PFAL 的功率时钟波形，发现三角形波形最优，单门能耗较静态 CMOS 降低 3.83 倍，4 位 Brent-Kung 加法器增益达 5.3 倍。
中文摘要 AI 辅助
绝热逻辑可以通过准可逆开关回收负载电容上存储的部分能量，但其在 FinFET 技术以及多吉赫兹频率下经波形优化的运行方式仍未得到充分探索。本研究在台积电 16 nm FinFET 工艺中研究了正反馈绝热逻辑（PFAL）。设计了一个功能完整的 PFAL 门库，并通过在功率时钟幅度、频率和波形形状上进行能量-延迟积优化，对其进行了验证和表征。功率时钟扫描表明，最小能量波形接近三角形而非传统梯形。优化后的单门 PFAL 单元相比等效静态 CMOS 门，能量最多可降低 3.83 倍，而正弦激励相比梯形激励可将能量最多提高 1.32 倍，并扩展了有效工作范围。随后，该门库被用于构建更大的组合电路，包括一个 2:1 多路复用器、一个 4 位纹波进位加法器以及一个 4 位 Brent-Kung 先行进位加法器。对于三角形功率时钟，先行进位加法器相比静态 CMOS 能量估算，增益最高可达 5.3 倍。
英文摘要
Adiabatic logic can recover part of the energy stored on load capacitances through quasi-reversible switching, but its waveform-optimized operation in FinFET technology and at multi-GHz frequencies remains underexplored. This work investigates Positive Feedback Adiabatic Logic (PFAL) in the TSMC 16 nm FinFET process. A functionally complete PFAL gate library is designed, verified, and characterised using energy-delay product optimization over power-clock amplitude, frequency, and waveform shape. The power-clock sweep shows that the minimum-energy waveform approaches a triangular shape rather than a conventional trapezoid. The optimized single-gate PFAL cells achieve up to 3.83x lower energy than equivalent static CMOS gates, while sinusoidal excitation improves energy by up to 1.32x compared with trapezoidal excitation and extends the valid operating range. The library is then used to construct larger combinational circuits, including a 2:1 multiplexer, a 4-bit ripple carry adder, and a 4-bit Brent-Kung carry look-ahead adder. The carry look-ahead adder reaches a gain of up to 5.3x compared with the static CMOS energy estimate for the triangular power-clock.
发表机构
- Eindhoven University of Technology（埃因霍温理工大学）
机构由 AI 辅助整理，请以论文原文为准。
