32位磁振子纹波进位加法器的数值模型
Numerical model for 32-bit magnonic ripple carry adder
摘要：
在基于CMOS的电子器件中，实现求和运算的最直接方法是使用纹波进位加法器（RCA）。磁振子学是研究自旋波及其量子磁振子数据处理的科学领域，最近提出了一种磁振子半加法器，可以被认为是最简单的磁振子集成电路。在这里，我们开发了一个计算模型的磁振子的基本块，使磁振子门和磁振子电路的设计和模拟的任意复杂性，并证明其功能的32位集成RCA的例子。它示出的RCA需要利用额外的再生器的基础上的磁振子定向耦合器与嵌入式放大器规范化的磁振子信号之间的半加法器。对大规模磁振子集成电路进行了基准测试。考虑到所有需要的放大器，基于30 nm的磁振子32位加法器的能量消耗可以低至961 aJ/操作。
英文摘要：
In CMOS-based electronics, the most straightforward way to implement a summation operation is to use the ripple carry adder (RCA). Magnonics, the field of science concerned with data processing by spin-waves and their quanta magnons, recently proposed a magnonic half-adder that can be considered as the simplest magnonic integrated circuit. Here, we develop a computation model for the magnonic basic blocks to enable the design and simulation of magnonic gates and magnonic circuits of arbitrary complexity and demonstrate its functionality on the example of a 32-bit integrated RCA. It is shown that the RCA requires the utilization of additional regenerators based on magnonic directional couplers with embedded amplifiers to normalize the magnon signals in-between the half-adders. The benchmarking of large-scale magnonic integrated circuits is performed. The energy consumption of 30 nm-based magnonic 32-bit adder can be as low as 961aJ per operation with taking into account all required amplifiers.
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