The development of CMOS pixel sensors with column parallel read-out and integrated zero-suppression has resulted in a full size, nearly 1 Megapixel, prototype with ~100 μs read-out time. Its performances are quite close to the ILD vertex detector specifications, showing that the sensor architecture can presumably be evolved to meet these specifications exactly.
Starting from the existing architecture and achieved performances, the paper will expose the details of how the sensor will be evolved in the coming 2-3 years in perspective of the ILD Detector Baseline Document, to be delivered in 2012. Two different devices are foreseen for this objective, one being optimized for the inner layers and their fast read-out requirement, while the other exploits the dimmed background in the outer layers to reduce the power consumption. The sensor evolution relies on a high resistivity epitaxial layer, on the use of an advanced CMOS process and on the combination of column-level ADCs with a pixel array. The paper will present how these aspects can be exploited to match the ILD VTX specifications.
A status of the development of 3D CMOS devices will be mentioned for completeness.
An R&D program on monolithic CMOS pixel sensors for application at the ILC has been started at LBNL. This program profits of significant synergies with other R&D activities on CMOS pixel sensors. The project activities after the first semester of the R&D program are reviewed.
This paper presents the design and results of detailed tests of a CMOS active pixel chip for charged particle detection with in-pixel charge storage for correlated double sampling and readout in rolling shutter mode at frequencies up to 25 MHz. This detector is developed in the framework of R&D for the Vertex Tracker for the International Linear Collider.
ISIS (In-situ Storage Imaging Sensor) is a novel CMOS sensor with multiple charge storage capability developed for the ILC vertex detector by the Linear Collider Flavour Identification (LCFI) collaboration. This paper reports test results for ISIS2, the second generation of ISIS sensors implemented in a 0.18 micron CMOS process. The local charge storage and charge transfer were unambiguously demonstrated.
The development of ultra-light pixelated ladders is motivated by the requirements of the ILD vertex detector at ILC. This paper summarizes three projects related to system integration. The PLUME project tackles the issue of assembling double-sided ladders. The SERWIETE project deals with a more innovative concept and consists in making single-sided unsupported ladders embedded in an extra thin plastic enveloppe. AIDA, the last project, aims at building a framework reproducing the experimental running conditions where sets of ladders could be tested.
This paper presents the design and results of detailed tests of a CMOS active pixel chip for charged particle detection with in-pixel charge storage for correlated double sampling and readout in rolling shutter mode at frequencies up to 25 MHz. This detector is developed in the framework of R&D for the Vertex Tracker for a future e+e- Linear Collider.
This paper reports results on a detailed study of charge collection and signal-to-noise performance of CMOS monolithic pixel sensors before and after back-thinning and their application in a pixel beam telescope for the ALS 1.5 GeV $e^-$ beam test facility.
A cluster imaging technique for Transmission Electron Microscopy with a direct detection CMOS pixel sensor is presented. Charge centre-of-gravity reconstruction for individual electron clusters improves the spatial resolution and thus the point spread function. Data collected with a CMOS sensor with 9.5 micron pixels show an improvement of a factor of two in point spread function to 2.7 micron at 300 keV and of a factor of three in the image contrast, compared to traditional bright field illumination.
A prototype of the CMOS pixel sensor named SUPIX-1 has been fabricated and tested in order to investigate the feasibility of a pixelated tracker for a proposed Higgs factory, namely, the Circular Electron-Positron Collider (CEPC). The sensor, taped out with a 180 nm CMOS Image Sensor (CIS) process, consists of nine different pixel arrays varying in pixel pitches, diode sizes and geometries in order to study the particle detection performance of enlarged pixels. The test was carried out with a Fe-55 radioactive source. Two soft X-ray peaks observed were used to calibrate the charge to voltage f…
The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$μ$m $\times$ 50$μ$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successi…
This paper presents the results of a study of the response of a test CMOS sensor with a radiation tolerant pixel cell design to 80 keV and 100 keV electrons. The point spread function is measured to be (13.0+/- 1.7) microns at 100 keV and (12.1 +/- 1.6) microns at 80 keV, for 20 micron pixels. Results agree well with values predicted by a Geant-4 and dedicated charge collection simulation.
This paper reviews the development of CMOS Monolithic Active Pixel Sensors (MAPS) for future vertex detectors. MAPS are developed in a standard CMOS technology. In the imaging field, where the technology found its first applications, they are also known as CMOS Image Sensors. The use of MAPS as a detector for particle physics was first proposed at the end of 1999. Since then, their good performance in terms of spatial resolution, efficiency, radiation hardness have been demonstrated and work is now well under way to deliver the first MAPS-based vertex detectors.
The upgrade to the High Luminosity Large Hadron Collider will pose unprecedented challenges to the tracking systems of all experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors. This article presents studies with a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer. The device under test is structured in smaller pixels than those of the attached read-out chip with information on t…
We have developed a prototype system for the ILC vertex detector based on DEPFET pixels. The system operates a 128x64 matrix (with ~35x25 square micron large pixels) and uses two dedicated microchips, the SWITCHER II chip for matrix steering and the CURO II chip for readout. The system development has been driven by the final ILC requirements which above all demand a detector thinned to 50 micron and a row wise read out with line rates of 20MHz and more. The targeted noise performance for the DEPFET technology is in the range of ENC=100 e-. The functionality of the system has been demonstrated…
Monolithic CMOS pixel sensors offer unprecedented opportunities for fast nano-imaging through direct electron detection in transmission electron microscopy. We present the design and a full characterisation of a CMOS pixel test structure able to withstand doses in excess of 1 MRad. Data collected with electron beams at various energies of interest in electron microscopy are compared to predictions of simulation and to 1.5 GeV electron data to disentagle the effect of multiple scattering. The point spread function measured with 300 keV electrons is (8.1 +/- 1.6) micron for 10 micron pixel and (…
We present results of a study of charged particle track and vertex reconstruction with a beam telescope made of four layers of 50 micron-thin CMOS monolithic pixel sensors using the 120 GeV protons at the FNAL Meson Test Beam Facility. We compare our results to the performance requirements of a future e+e- linear collider in terms of particle track extrapolation and vertex reconstruction accuracies.
Hybrid pixel detectors have been invented for the LHC to make tracking and vertexing possible at all in LHC's radiation intense environment. The LHC pixel detectors have meanwhile very successfully fulfilled their promises and R\&D for the planned HL-LHC upgrade is in full swing, targeting even higher ionising doses and non-ionising fluences. In terms of rate and radiation tolerance hybrid pixels are unrivaled. But they have disadvantages as well, most notably material thickness, production complexity, and cost. Meanwhile also active pixel sensors (DEPFET, MAPS) have become real pixel detector…
We are investigating the feasibility of using CMOS foundries to fabricate silicon detectors, both for pixels and for large-area strip sensors. The availability of multi-layer routing will provide the freedom to optimize the sensor geometry and the performance, with biasing structures in poly-silicon layers and MIM-capacitors allowing for AC coupling. A prototyping production of strip test-structures and RD53A compatible pixel sensors was recently completed at LFoundry in a 150$\,$nm CMOS process. This paper will focus on the characterization of irradiated and non-irradiated pixel modules, comp…
We report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35um CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that…
CMOS pixel sensors with a small collection electrode combine the advantages of a small sensor capacitance with the advantages of a fully monolithic design. The small sensor capacitance results in a large ratio of signal-to-noise and a low analogue power consumption, while the monolithic design reduces the material budget, cost and production effort. However, the low electric field in the pixel corners of such sensors results in an increased charge collection time, that makes a fully efficient operation after irradiation and a timing resolution in the order of nanoseconds challenging for pixel …
Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. Depleted fully monolithic CMOS pixels with fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototy…
The International Linear Collider (ILC) is a project of an electron-positron (e+e-) linear collider with the centre-of-mass energy of 200-500 GeV. Monolithic Active Pixel Sensors (MAPS) are one of the proposed silicon pixel detector concepts for the ILC vertex detector (VTX). Basic characteristics of two MAPS pixel matrices MIMOSA-5 (17 $μ$m pixel pitch) and MIMOSA-18 (10 $μ$m pixel pitch) are studied and compared (pedestals, noises, calibration of the ADC-to-electron conversion gain, detector efficiency and charge collection properties). The e+e- collisions at the ILC will be accompanied by i…
In this paper we present a novel, quadruple well process developed in a modern 0.18mu CMOS technology called INMAPS. On top of the standard process, we have added a deep P implant that can be used to form a deep P-well and provide screening of N-wells from the P-doped epitaxial layer. This prevents the collection of radiation-induced charge by unrelated N-wells, typically ones where PMOS transistors are integrated. The design of a sensor specifically tailored to a particle physics experiment is presented, where each 50mu pixel has over 150 PMOS and NMOS transistors. The sensor has been fabrica…
We present the detailed study of the digital readout of Topmetal-II- CMOS pixel direct charge sensor. Topmetal-II- is an integrated sensor with an array of 72X72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators with individually DAC settable thresholds in each pixel. The hits are read out via a column-based priority logic structure, retaining both hit location a…
This article reports the first operation of a double-sided CMOS pixelated ladder in a collider experiment, namely in the inner tracker volume of the Belle II experiment during the Phase 2 run of the SuperKEKB collider. Design and integration of the detector system in the experiment interaction region is first described. The two modules operated almost continuously during slightly more than four months, recording data for the monitoring of the hit rate close to beams. Details of the off-line data analysis are provided and a method to estimate particle momentum from the 2 hits measured per cross…
This paper focuses on the conversion gain (CG) of pixels implementing pinned photo-diodes (PPD) and in-pixel voltage follower in standard CMOS image sensor (CIS) process. An overview of the CG expression and its impact on the noise performance of the CIS readout chain is presented. CG enhancement techniques involving process refinements and pure circuit design and pixel scheme optimization are introduced. The implementation of these techniques in a 180 nm CIS process demonstrates a progressive enhancement of the CG by more than a factor 3 with respect to a standard reference pixel from the sam…
High-Voltage Monolithic Active Pixel Sensors (HV-MAPS) based on the 180 nm HV-CMOS process have been proposed to realize thin, fast and highly integrated pixel sensors. The MuPix7 prototype, fabricated in the commercial AMS H18 process, features a fully integrated on-chip readout, i.e. hit-digitization, zero suppression and data serialization. It is the first fully monolithic HV-CMOS pixel sensor that has been tested for the use in high irradiation environments like HL-LHC. We present results from laboratory and test beam measurements of MuPix7 prototypes irradiated with neutrons (up to $5.0\c…
The MuPix7 chip is a monolithic HV-CMOS pixel chip, thinned down to 50 μm. It provides continuous self-triggered, non-shuttered readout at rates up to 30 Mhits/chip of 3x3 mm^2 active area and a pixel size of 103x80 μm^2. The hit efficiency depends on the chosen working point. Settings with a power consumption of 300 mW/cm^2 allow for a hit efficiency >99.5%. A time resolution of 14.2 ns (Gaussian sigma) is achieved. Latest results from 2016 test beam campaigns are shown.
The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a de…
Depleted CMOS active sensors (DMAPS) are being developed for high-energy particle physics experiments in high radiation environments, such as in the ATLAS High Luminosity Large Hadron Collider (HL-LHC). Since charge collection by drift is mandatory for harsh radiation environment, the application of high bias voltage to high resistive sensor material is needed. In this work, a prototype of a DMAPS was fabricated in a 150nm CMOS process on a substrate with a resistivity of >2 kΩcm that was thinned to 100 μm. Full depletion occurs around 20V, which is far below the breakdown voltage of 110 V. A …
This paper contains a compilation of parameters influencing the charge collection process extracted from a comprehensive study of partially depleted Monolithic Active Pixel Sensors with small (<25 um$^2$) collection electrodes fabricated in the TowerJazz 180 nm CMOS process. These results gave guidance for the optimisation of the diode implemented in ALPIDE, the chip used in the second generation Inner Tracking System of ALICE, and serve as reference for future simulation studies of similar devices. The studied parameters include: reverse substrate bias, epitaxial layer thickness, charge colle…
Depleted monolithic CMOS active pixel sensors (DMAPS) have been developed in order to demonstrate their suitability as pixel detectors in the outer layers of a toroidal LHC apparatus inner tracker (ATLAS ITk) pixel detector in the high-luminosity large hadron collider (HL-LHC). Two prototypes have been fabricated using 150 nm CMOS technology on high resistivity (> 2 k$Ω$ $cm^2$) wafers. The chip size is equivalent to that of the current ATLAS pixel detector readout chip. One of the prototypes is used for detailed characterization of the sensor and the analog readout of the DMAPS. The other is …
In this work we investigated a method to determine time walk in an active silicon pixel sensor prototype using Edge-TCT with infrared laser charge injection. Samples were investigated before and after neutron irradiation to 5e14 neq/cm2. Threshold, noise and calibration of the analogue front end were determined with external charge injection. A spatially sensitive measurement of collected charge and time walk was carried out with Edge-TCT, showing a uniform charge collection and output delay in pixel centre. On pixel edges charge sharing was observed due to finite beam width resulting in small…
We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm technology, featuring a $32 \times 32$ pixel matrix with a pitch of $55 ~ μm$. Timespot1 is the first small-size prototype, conceived to readout fine-pitch pixels with single-hit time resolution below $50 ~ ps_\text{rms}$ and input rates of several hundreds of kilohertz per pixel. Such experimental conditions will be typical of the next generation of high-luminosity collider experiments, from the LHC run5 and beyond. Each pixel of the ASIC includes a charge amplifier, a discriminator, and a Time-to-Digit…
We have operated a Medipix2 CMOS readout chip, with amplifying, shaping and charge discriminating front-end electronics integrated on the pixel-level, as a highly segmented direct charge collecting anode in a three-stage gas electron multiplier (Triple-GEM) to detect the ionization from $^{55}$Fe X-rays and electrons from $^{106}$Ru. The device allows to perform moderate energy spectroscopy measurements (20 % FWHM at 5.9 keV $X$-rays) using only digital readout and two discriminator thresholds. Being a truly 2D-detector, it allows to observe individual clusters of minimum ionizing charged part…
The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a deplet…
In the context of the studies of the ATLAS High Luminosity LHC programme, radiation tolerant pixel detectors in CMOS technologies are investigated. To evaluate the effects of substrate resistivity on CMOS sensor performance, the H35DEMO demonstrator, containing different diode and amplifier designs, was produced in ams H35 HV-CMOS technology using four different substrate resistivities spanning from $\mathrm{80}$ to $\mathrm{1000~Ω\cdot cm}$. A glueing process using a high-precision flip-chip machine was developed in order to capacitively couple the sensors to FE-I4 Readout ASIC using a thin l…
HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the $4^{\mathrm{th}}$ generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between $1\cdot 10^{14}$ and $5\cdot 10^{15}$ 1-MeV-n$_\textrm{eq}$/cm$^2$. T…
Over the past few years we have developed, in collaboration with the SARNOFF Corporation, a design of a Monolithic CMOS Pixel Detector for ILC Vertex Detectors. The unique feature of this design is that each hit is accompanied by a time tag with sufficient precision to assign each hit to a particular bunch crossing of the ILC (thus the name Chronopixel). This reduces the occupancy even in the innermost Vertex Detector layer to negligible levels, allowing a robust Vertex Detector even in the case that the backgrounds in the ILC are higher than presently estimated.
Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s employing silicon substrate with a thin epitaxial layer in which deposited charge is collected by disordered diffusion rather than by drift in an electric field. As a consequence the signal is small and slow, and the radiation tolerance is below the requirements for LHC experiments by factors of 100 to 1000. We developed fully depleted (D)MAPS pixel sensors employing a 150 nm CMOS technology and using a high resistivity substrate as well as a high biasing voltage. The development has been carried out in three subse…
The RD50-CMOS group aims to design and study High Voltage CMOS (HVCMOS) chips for use in a high radiation environment. Currently, measurements are performed on RD50-MPW2 chip, the second prototype developed by this group. The active matrix of the prototype consists of 8x8 pixels with analog front end. Details of the analog front end and simulations have been already published earlier. This contribution focuses on the Caribou based readout system of the active matrix. Each pixel of the active matrix can be readout one after the other. Relevant aspects of hardware, firmware and software are intr…
This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150\,nm CMOS process. DMAPS exploit high voltage and/or high resistivity inclusion of modern CMOS technologies to achieve substantial depletion in the sensing volume. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade in 2025 for the High Luminosity Large Hadron Collider (HL-LHC). This type of devices has a lower production cost and lower materia…
The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 um CMOS technology, and provides outstanding performance in terms of s…
Charge collection properties of depleted CMOS pixel detector prototypes produced on p-type substrate of 2 k$Ω$cm initial resistivity (by LFoundry 150 nm process) were studied using Edge-TCT method before and after neutron irradiation. The test structures were produced for investigation of CMOS technology in tracking detectors for experiments at HL-LHC upgrade. Measurements were made with passive detector structures in which current pulses induced on charge collecting electrodes could be directly observed. Thickness of depleted layer was estimated and studied as function of neutron irradiation …
CMOS Monolithic Active Pixel Sensors (MAPS) are proposed as a technology for various vertex detectors in nuclear and particle physics. We discuss the mechanisms of ionizing radiation damage on MAPS hosting the the dead time free, so-called self bias pixel. Moreover, we discuss radiation hardened sensor designs which allow operating detectors after exposing them to irradiation doses above 1 Mrad
A novel design for a silicon-tungsten electromagnetic calorimeter is described, based on Monolithic Active Pixel Sensors (MAPS). A test sensor with a pixel size of 50x50 um2 has been fabricated in July 2007. The simulation of the physical sensor is done using a detailed three-dimensional charge spread algorithm. Physics studies of the sensor are done including a digitisation algorithm taking into account the charge sharing, charge collection efficiency, noise, and dead areas. The influence of the charge sharing effect is found to be important and hence needs to be measured precisely.
A 1M- and a 4M-pixel monolithic CMOS active pixel sensor with 9.5x9.5 micron^2 pixels have been developed for direct imaging in transmission electron microscopy as part of the TEAM project. We present the design and a full characterisation of the detector. Data collected with electron beams at various energies of interest in electron microscopy are used to determine the detector response. Data are compared to predictions of simulation. The line spread function measured with 80 keV and 300 keV electrons is (12.1+/-0.7) micron and (7.4+/-0.6) micron, respectively, in good agreement with our simu…
The radiation hardness of passive CMOS pixel sensors fabricated in 150 nm LFoundry technology is investigated. CMOS process lines are especially of interest for large-scale silicon detectors as they offer high production throughput at comparatively low cost. Moreover, several features like poly-silicon resistors, MIM-capacitors and several metal layers are available which can help enhance the sensor design. The performance of a 100 $\mathrmμ$m thin passive CMOS sensor with a pixel pitch of 50 $\mathrmμ$m at different irradiation levels, 5 $\times$ 10$^{15}$n$_{\mathrm{eq}}$cm$^{-2}$ and 1 $\ti…
Development of a Neutron Imager using CMOS Pixelated Sensor
The University of Tokyo（东京大学）；High Energy Accelerator Research Organization (KEK)（高能加速器研究机构（KEK））；The Graduate University for Advanced Studies (SOKENDAI)（高级研究院（SOKENDAI））；Tohoku University（东北大学）；Shiga University（滋贺大学）
Combining electrostatic field simulations with Monte Carlo methods enables realistic modeling of the detector response for novel monolithic silicon detectors with strongly non-linear electric fields. Both the precise field description and the inclusion of Landau fluctuations and production of secondary particles in the sensor are crucial ingredients for the understanding and reproduction of detector characteristics. In this paper, a CMOS pixel sensor with small collection electrode design, implemented in a high-resistivity epitaxial layer, is simulated by integrating a detailed electric field …
The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial $180$ nm HV-CMOS process and contains a matrix of $128\times128$ square pixels with $25$ $μ$m pitch. First prototypes have been produced with a standard resistivity of $\sim20$ $Ω$cm for the substrate and tested in standalone mode.…
In this paper, an in-pixel chopping technique to reduce the low-frequency or 1/f noise of the source follower (SF) transistor in an active pixel sensor (APS) is presented. The SF low-frequency noise is modulated at higher frequencies through chopping, implemented inside the pixel, and in later stage eliminated using low-pass filtering. To implement the chopping, the conventional 3T APS architecture is modified, with only one additional transistor of minimum size per pixel. Reduction in the noise also enhances the dynamic range (DR) of the image sensor. The test circuit is fabricated in UMC 0.1…
Edge-TCT and charge collection measurements with passive test structures made in LFoundry 150 nm CMOS process on p-type substrate with initial resistivity of over 3 k$Ω$cm are presented. Measurements were made before and after irradiation with reactor neutrons up to 2$\cdot$10$^{15}$ n$_{\mathrm{eq}}$/cm$^2$. Two sets of devices were investigated: unthinned (700 $μ$m) with substrate biased through the implant on top and thinned (200 $μ$m) with processed and metallised back plane. Depleted depth was estimated with Edge-TCT and collected charge was measured with $^{90}$Sr source using an externa…
